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20a3d2184f
Summary: Local values are constants, global addresses, and stack addresses that can't be folded into the instruction that uses them. For example, when storing the address of a global variable into memory, we need to materialize that address into a register. FastISel doesn't want to materialize any given local value more than once, so it generates all local value materialization code at EmitStartPt, which always dominates the current insertion point. This allows it to maintain a map of local value registers, and it knows that the local value area will always dominate the current insertion point. The downside is that local value instructions are always emitted without a source location. This is done to prevent jumpy line tables, but it means that the local value area will be considered part of the previous statement. Consider this C code: call1(); // line 1 ++global; // line 2 ++global; // line 3 call2(&global, &local); // line 4 Today we end up with assembly and line tables like this: .loc 1 1 callq call1 leaq global(%rip), %rdi leaq local(%rsp), %rsi .loc 1 2 addq $1, global(%rip) .loc 1 3 addq $1, global(%rip) .loc 1 4 callq call2 The LEA instructions in the local value area have no source location and are treated as being on line 1. Stepping through the code in a debugger and correlating it with the assembly won't make much sense, because these materializations are only required for line 4. This is actually problematic for the VS debugger "set next statement" feature, which effectively assumes that there are no registers live across statement boundaries. By sinking the local value code into the statement and fixing up the source location, we can make that feature work. This was filed as https://bugs.llvm.org/show_bug.cgi?id=35975 and https://crbug.com/793819. This change is obviously not enough to make this feature work reliably in all cases, but I felt that it was worth doing anyway because it usually generates smaller, more comprehensible -O0 code. I measured a 0.12% regression in code generation time with LLC on the sqlite3 amalgamation, so I think this is worth doing. There are some special cases worth calling out in the commit message: 1. local values materialized for phis 2. local values used by no-op casts 3. dead local value code Local values can be materialized for phis, and this does not show up as a vreg use in MachineRegisterInfo. In this case, if there are no other uses, this patch sinks the value to the first terminator, EH label, or the end of the BB if nothing else exists. Local values may also be used by no-op casts, which adds the register to the RegFixups table. Without reversing the RegFixups map direction, we don't have enough information to sink these instructions. Lastly, if the local value register has no other uses, we can delete it. This comes up when fastisel tries two instruction selection approaches and the first materializes the value but fails and the second succeeds without using the local value. Reviewers: aprantl, dblaikie, qcolombet, MatzeB, vsk, echristo Subscribers: dotdash, chandlerc, hans, sdardis, amccarth, javed.absar, zturner, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D43093 llvm-svn: 327581
138 lines
3.1 KiB
LLVM
138 lines
3.1 KiB
LLVM
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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define void @t0(i32 %a) nounwind {
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entry:
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; CHECK: t0
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; CHECK: str {{w[0-9]+}}, [sp, #12]
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; CHECK-NEXT: ldr [[REGISTER:w[0-9]+]], [sp, #12]
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; CHECK-NEXT: str [[REGISTER]], [sp, #12]
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; CHECK: ret
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr
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%tmp = load i32, i32* %a.addr
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store i32 %tmp, i32* %a.addr
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ret void
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}
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define void @t1(i64 %a) nounwind {
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; CHECK: t1
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; CHECK: str {{x[0-9]+}}, [sp, #8]
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; CHECK-NEXT: ldr [[REGISTER:x[0-9]+]], [sp, #8]
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; CHECK-NEXT: str [[REGISTER]], [sp, #8]
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; CHECK: ret
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%a.addr = alloca i64, align 4
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store i64 %a, i64* %a.addr
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%tmp = load i64, i64* %a.addr
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store i64 %tmp, i64* %a.addr
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ret void
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}
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define zeroext i1 @i1(i1 %a) nounwind {
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entry:
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; CHECK: @i1
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; CHECK: and w0, w0, #0x1
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; CHECK: strb w0, [sp, #15]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: and w0, w0, #0x1
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; CHECK: and w0, w0, #0x1
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; CHECK: add sp, sp, #16
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; CHECK: ret
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%a.addr = alloca i1, align 1
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store i1 %a, i1* %a.addr, align 1
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%0 = load i1, i1* %a.addr, align 1
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ret i1 %0
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}
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define i32 @t2(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: ldur w0, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -1
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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define i32 @t3(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: ldur w0, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -64
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%1 = load i32, i32* %0, align 4
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ret i32 %1
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}
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define void @t4(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t4:
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; CHECK: stur wzr, [x0, #-4]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -1
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t5(i32 *%ptr) nounwind {
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entry:
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; CHECK-LABEL: t5:
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; CHECK: stur wzr, [x0, #-256]
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; CHECK: ret
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%0 = getelementptr i32, i32 *%ptr, i32 -64
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store i32 0, i32* %0, align 4
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ret void
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}
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define void @t6() nounwind {
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; CHECK: t6
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; CHECK: brk #0x1
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tail call void @llvm.trap()
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ret void
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}
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declare void @llvm.trap() nounwind
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define void @ands(i32* %addr) {
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; CHECK-LABEL: ands:
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; CHECK: tst [[COND:w[0-9]+]], #0x1
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; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x2
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; CHECK-NEXT: orr w{{[0-9]+}}, wzr, #0x1
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; CHECK-NEXT: csel [[COND]],
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entry:
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%cond91 = select i1 undef, i32 1, i32 2
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store i32 %cond91, i32* %addr, align 4
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ret void
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}
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define i64 @mul_umul(i64 %arg) {
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; CHECK-LABEL: mul_umul:
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; CHECK: mul x{{[0-9]+}}, [[ARG1:x[0-9]+]], [[ARG2:x[0-9]+]]
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; CHECK-NEXT: umulh x{{[0-9]+}}, [[ARG1]], [[ARG2]]
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entry:
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%sub.ptr.div = sdiv exact i64 %arg, 8
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%tmp = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %sub.ptr.div, i64 8)
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%tmp1 = extractvalue { i64, i1 } %tmp, 0
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ret i64 %tmp1
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}
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declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
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define void @logicalReg() {
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; Make sure we generate a logical reg = reg, reg instruction without any
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; machine verifier errors.
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; CHECK-LABEL: logicalReg:
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; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
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; CHECK: ret
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entry:
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br i1 undef, label %cond.end, label %cond.false
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cond.false:
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%cond = select i1 undef, i1 true, i1 false
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br label %cond.end
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cond.end:
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%cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
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ret void
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}
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