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fb62a27499
This reverses instcombine's demanded bits' transform which always tries to clear bits in constants. As noted in PR35792 and shown in the test diffs: https://bugs.llvm.org/show_bug.cgi?id=35792 ...we can do better in codegen by trying to form -1. The x86 sub test shows a missed opportunity. I did investigate changing instcombine's behavior, but it would be more work to change canonicalization in IR. Clearing bits / shrinking constants can allow killing instructions, so we'd have to figure out how to not regress those cases. Differential Revision: https://reviews.llvm.org/D42986 llvm-svn: 324839
17 lines
474 B
LLVM
17 lines
474 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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define i64 @sub1_disguised_constant(i64 %x) {
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; CHECK-LABEL: sub1_disguised_constant:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub w8, w0, #1 // =1
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; CHECK-NEXT: and w8, w0, w8
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; CHECK-NEXT: and x0, x8, #0xffff
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; CHECK-NEXT: ret
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%a1 = and i64 %x, 65535
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%a2 = add i64 %x, 65535
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%r = and i64 %a1, %a2
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ret i64 %r
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}
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