mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-30 07:22:55 +01:00
29127b8825
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
llvm-svn: 10461
445 lines
13 KiB
C++
445 lines
13 KiB
C++
//===-- MachineInstr.cpp --------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Value.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/MRegisterInfo.h"
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namespace llvm {
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class TargetInstrInfo.
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//
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// FIXME: This should be a property of the target so that more than one target
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// at a time can be active...
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//
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extern const TargetInstrDescriptor *TargetInstrDescriptors;
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned numOperands)
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: opCode(OpCode),
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opCodeFlags(0),
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operands(numOperands, MachineOperand()),
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numImplicitRefs(0)
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{
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}
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/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
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/// not a resize for them. It is expected that if you use this that you call
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/// add* methods below to fill up the operands, instead of the Set methods.
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/// Eventually, the "resizing" ctors will be phased out.
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///
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MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
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bool XX, bool YY)
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: opCode(Opcode),
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opCodeFlags(0),
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numImplicitRefs(0)
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{
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operands.reserve(numOperands);
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}
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
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unsigned numOperands)
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: opCode(Opcode),
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opCodeFlags(0),
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numImplicitRefs(0)
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{
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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operands.reserve(numOperands);
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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// OperandComplete - Return true if it's illegal to add a new operand
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bool MachineInstr::OperandsComplete() const
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{
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int NumOperands = TargetInstrDescriptors[opCode].numOperands;
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if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
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return true; // Broken: we have all the operands of this instruction!
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return false;
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}
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//
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// Support for replacing opcode and operands of a MachineInstr in place.
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// This only resets the size of the operand vector and initializes it.
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// The new operands must be set explicitly later.
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//
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void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
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{
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assert(getNumImplicitRefs() == 0 &&
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"This is probably broken because implicit refs are going to be lost.");
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opCode = Opcode;
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operands.clear();
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operands.resize(numOperands, MachineOperand());
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}
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void MachineInstr::SetMachineOperandVal(unsigned i,
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MachineOperand::MachineOperandType opTy,
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Value* V) {
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assert(i < operands.size()); // may be explicit or implicit op
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operands[i].opType = opTy;
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operands[i].value = V;
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operands[i].regNum = -1;
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}
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void
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MachineInstr::SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue)
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{
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assert(i < getNumOperands()); // must be explicit op
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assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
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"immed. constant cannot be defined");
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operands[i].opType = operandType;
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operands[i].value = NULL;
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operands[i].immedVal = intValue;
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operands[i].regNum = -1;
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operands[i].flags = 0;
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}
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void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
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assert(i < getNumOperands()); // must be explicit op
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operands[i].opType = MachineOperand::MO_MachineRegister;
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operands[i].value = NULL;
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operands[i].regNum = regNum;
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}
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void
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MachineInstr::SetRegForOperand(unsigned i, int regNum)
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{
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assert(i < getNumOperands()); // must be explicit op
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operands[i].setRegForValue(regNum);
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}
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void
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MachineInstr::SetRegForImplicitRef(unsigned i, int regNum)
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{
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getImplicitOp(i).setRegForValue(regNum);
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}
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// Substitute all occurrences of Value* oldVal with newVal in all operands
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// and all implicit refs.
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// If defsOnly == true, substitute defs only.
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unsigned
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MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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bool defsOnly, bool notDefsAndUses,
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bool& someArgsWereIgnored)
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{
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assert((!defsOnly || !notDefsAndUses) &&
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"notDefsAndUses is irrelevant if defsOnly == true.");
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unsigned numSubst = 0;
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// Substitute operands
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for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
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if (*O == oldVal)
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if (!defsOnly ||
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notDefsAndUses && (O.isDef() && !O.isUse()) ||
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!notDefsAndUses && O.isDef())
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{
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O.getMachineOperand().value = newVal;
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++numSubst;
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}
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else
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someArgsWereIgnored = true;
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// Substitute implicit refs
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for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
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if (getImplicitRef(i) == oldVal)
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if (!defsOnly ||
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notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
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!notDefsAndUses && getImplicitOp(i).isDef())
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{
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getImplicitOp(i).value = newVal;
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++numSubst;
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}
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else
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someArgsWereIgnored = true;
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return numSubst;
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}
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void
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MachineInstr::dump() const
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{
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std::cerr << " " << *this;
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}
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static inline std::ostream&
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OutputValue(std::ostream &os, const Value* val)
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{
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os << "(val ";
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os << (void*) val; // print address always
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if (val && val->hasName())
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os << " " << val->getName() << ")"; // print name also, if available
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return os;
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}
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static inline void OutputReg(std::ostream &os, unsigned RegNo,
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const MRegisterInfo *MRI = 0) {
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if (MRI) {
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if (RegNo < MRegisterInfo::FirstVirtualRegister)
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os << "%" << MRI->get(RegNo).Name;
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else
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os << "%reg" << RegNo;
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} else
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os << "%mreg(" << RegNo << ")";
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}
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static void print(const MachineOperand &MO, std::ostream &OS,
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const TargetMachine &TM) {
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const MRegisterInfo *MRI = TM.getRegisterInfo();
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bool CloseParen = true;
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if (MO.isHiBits32())
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OS << "%lm(";
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else if (MO.isLoBits32())
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OS << "%lo(";
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else if (MO.isHiBits64())
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OS << "%hh(";
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else if (MO.isLoBits64())
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OS << "%hm(";
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else
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CloseParen = false;
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.getVRegValue()) {
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OS << "%reg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg())
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OS << "==";
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}
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getAllocatedRegNum(), MRI);
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getAllocatedRegNum(), MRI);
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum(), MRI);
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp: {
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "bb<"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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}
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if (CloseParen)
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OS << ")";
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}
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void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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unsigned StartOp = 0;
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// Specialize printing if op#0 is definition
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if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
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llvm::print(getOperand(0), OS, TM);
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OS << " = ";
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++StartOp; // Don't print this operand again!
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}
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OS << TM.getInstrInfo().getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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if (i != StartOp)
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OS << ",";
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OS << " ";
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llvm::print(mop, OS, TM);
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if (mop.isDef())
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if (mop.isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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}
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// code for printing implicit references
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if (getNumImplicitRefs()) {
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OS << "\tImplicitRefs: ";
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for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
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OS << "\t";
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OutputValue(OS, getImplicitRef(i));
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if (getImplicitOp(i).isDef())
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if (getImplicitOp(i).isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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}
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}
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OS << "\n";
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}
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std::ostream &operator<<(std::ostream& os, const MachineInstr& MI)
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{
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os << TargetInstrDescriptors[MI.opCode].Name;
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for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
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os << "\t" << MI.getOperand(i);
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if (MI.getOperand(i).isDef())
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if (MI.getOperand(i).isUse())
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os << "<d&u>";
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else
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os << "<d>";
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}
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// code for printing implicit references
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unsigned NumOfImpRefs = MI.getNumImplicitRefs();
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if (NumOfImpRefs > 0) {
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os << "\tImplicit: ";
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for (unsigned z=0; z < NumOfImpRefs; z++) {
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OutputValue(os, MI.getImplicitRef(z));
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if (MI.getImplicitOp(z).isDef())
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if (MI.getImplicitOp(z).isUse())
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os << "<d&u>";
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else
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os << "<d>";
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os << "\t";
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}
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}
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return os << "\n";
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}
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std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
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{
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if (MO.isHiBits32())
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OS << "%lm(";
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else if (MO.isLoBits32())
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OS << "%lo(";
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else if (MO.isHiBits64())
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OS << "%hh(";
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else if (MO.isLoBits64())
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OS << "%hm(";
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switch (MO.getType())
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{
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case MachineOperand::MO_VirtualRegister:
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getAllocatedRegNum());
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if (MO.getVRegValue()) {
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if (MO.hasAllocatedReg()) OS << "==";
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OS << "%vreg";
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OutputValue(OS, MO.getVRegValue());
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}
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getAllocatedRegNum());
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum());
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp:
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{
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "bb<"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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if (MO.flags &
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(MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
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MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
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OS << ")";
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return OS;
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}
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} // End llvm namespace
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