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llvm-mirror/test/TableGen/isa.td
Nicolai Haehnle f6565225c2 TableGen: add !isa operation
Change-Id: Iddb724c3ae706d82933a2d82c91d07e0e36b30e3

Differential revision: https://reviews.llvm.org/D44105

llvm-svn: 327117
2018-03-09 12:24:06 +00:00

40 lines
562 B
TableGen

// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: --- Defs ---
// CHECK: def X0 {
// CHECK: int ret = 0;
// CHECK: }
// CHECK: def X1 {
// CHECK: int ret = 1;
// CHECK: }
// CHECK: def Y0 {
// CHECK: int ret = 0;
// CHECK: }
// CHECK: def Y1 {
// CHECK: int ret = 11;
// CHECK: }
class A<int dummy>;
class B<int num> : A<num> {
int Num = num;
}
class X<A a> {
int ret = !isa<B>(a);
}
class Y<A a> {
int ret = !if(!isa<B>(a), !cast<B>(a).Num, 0);
}
def X0 : X<A<0>>;
def X1 : X<B<0>>;
def Y0 : Y<A<10>>;
def Y1 : Y<B<11>>;