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llvm-mirror/test/MC/Disassembler
Krzysztof Parzyszek 7aefd2fd47 [Hexagon] Adding gp+ to the syntax of gp-relative instructions
Patch by Colin LeMahieu.

llvm-svn: 294258
2017-02-06 23:18:57 +00:00
..
AArch64 AArch64: TableGenerate system instruction operands. 2016-07-05 21:23:04 +00:00
AMDGPU Reapply [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8. 2017-01-30 21:59:21 +00:00
ARM [ARM] Saturation instructions are DSP-only 2016-07-25 22:25:25 +00:00
Hexagon [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
Lanai [lanai] Add Lanai backend. 2016-03-28 13:09:54 +00:00
Mips [mips] Correct c.cond.fmt instruction definition. 2017-01-16 13:55:58 +00:00
PowerPC Add some Book-E instructions to the asm parser and printer. 2017-01-29 04:55:57 +00:00
Sparc This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SystemZ [SystemZ] Support remaining atomic instructions 2016-12-02 18:24:16 +00:00
X86 [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument. 2017-02-05 18:33:31 +00:00
XCore