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2f56005d71
The VGPR component is a 32-bit offset, not 64-bits. I'm not sure what the correct syntax is for this. This maintains the vaddr position and leaves saddr in the end "off" position. This is particularly terrible for stores, since the operand order is now <vgpr offset>, <data>, <sgpr base>, splitting the pointer operands. I suppose this is a logical consequence from the mistake of not putting the data operand first. I'm not sure what sp3 does.
391 lines
14 KiB
YAML
391 lines
14 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass=si-peephole-sdwa -o - %s | FileCheck -check-prefix=GFX9 %s
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# test for 3 consecutive _sdwa's
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# GFX9-LABEL: name: test1_add_co_sdwa
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# GFX9: = nsw V_ADD_CO_U32_sdwa
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# GFX9-NEXT: = nuw V_ADDC_U32_e32
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# GFX9: V_ADD_CO_U32_sdwa
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# GFX9-NEXT: V_ADDC_U32_e32
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# GFX9: V_ADD_CO_U32_sdwa
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# GFX9-NEXT: V_ADDC_U32_e32
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---
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name: test1_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = nsw V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%64:vgpr_32, dead %66:sreg_64_xexec = nuw V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
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%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
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%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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%171:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%173:vgpr_32, %175:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %171, 0, implicit $exec
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%174:vgpr_32, dead %176:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %175, 0, implicit $exec
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%172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %172, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for VCC interference on sdwa, should generate 1 xform only
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# GFX9-LABEL: name: test2_add_co_sdwa
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# GFX9: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e32
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9-NOT: V_ADDC_U32_e32
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---
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name: test2_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
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%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
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%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
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%64:vgpr_32, dead %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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%161:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%163:vgpr_32, %165:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %161, 0, implicit $exec
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%164:vgpr_32, dead %166:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %165, 0, implicit $exec
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%162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %162, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for CarryOut used, should reject
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# GFX9-LABEL: name: test3_add_co_sdwa
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# GFX9: V_ADD_CO_U32_e64
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# GFX9: V_ADDC_U32_e64
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9-NOT: V_ADDC_U32_e32
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---
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name: test3_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, killed %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for CarryIn used more than once, should reject
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# GFX9-LABEL: name: test4_add_co_sdwa
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# GFX9: V_ADD_CO_U32_e64
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# GFX9: V_ADDC_U32_e64
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9-NOT: V_ADDC_U32_e32
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---
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name: test4_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for simple example, should generate sdwa
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# GFX9-LABEL: name: test5_add_co_sdwa
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# GFX9: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e32
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---
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name: test5_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for V_ADD_CO_U32_e64 only, should reject
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# GFX9-LABEL: name: test6_add_co_sdwa
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# GFX9: V_ADD_CO_U32_e64
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9-NOT: V_ADDC_U32_e32
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---
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name: test6_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for V_ADDC_U32_e64 only, should reject
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# GFX9-LABEL: name: test7_add_co_sdwa
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# GFX9: V_ADDC_U32_e64
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9-NOT: V_ADDC_U32_e32
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---
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name: test7_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%24:sreg_64_xexec = COPY $sgpr0_sgpr1
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %24, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %30.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for $vcc defined between two adds, should not generate
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# GFX9-LABEL: name: test8_add_co_sdwa
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e64
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---
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name: test8_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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$vcc = COPY %30
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%31:vreg_64 = COPY $vcc
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for non dead $vcc, should not generate
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# GFX9-LABEL: name: test9_add_co_sdwa
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e64
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---
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name: test9_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%30:vreg_64 = COPY $sgpr0_sgpr1
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$vcc = COPY %30
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%31:vreg_64 = COPY $vcc
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for def $vcc_lo, should not generate
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# GFX9-LABEL: name: test10_add_co_sdwa
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e64
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---
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name: test10_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%30:vreg_64 = COPY $sgpr0_sgpr1
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$vcc_lo = COPY %30.sub0
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%31:vgpr_32 = COPY $vcc_lo
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%32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for read $vcc_hi, should not generate
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# GFX9-LABEL: name: test11_add_co_sdwa
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e64
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---
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name: test11_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%30:vreg_64 = COPY $sgpr0_sgpr1
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$vcc_hi = COPY %30.sub0
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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%31:vgpr_32 = COPY $vcc_hi
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%32:vreg_64 = REG_SEQUENCE %31, %subreg.sub0, %23, %subreg.sub1
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %32.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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...
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# test for $vcc defined and used between adds, should not generate
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# GFX9-LABEL: name: test12_add_co_sdwa
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# GFX9-NOT: V_ADD_CO_U32_sdwa
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# GFX9: V_ADDC_U32_e64
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---
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name: test12_add_co_sdwa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%1' }
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0_sgpr1
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%1:sgpr_64 = COPY $sgpr0_sgpr1
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%0:vgpr_32 = COPY $vgpr0
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%22:sreg_32_xm0 = S_MOV_B32 255
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%30:vreg_64 = COPY $sgpr0_sgpr1
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%23:vgpr_32 = V_AND_B32_e32 %22, %0, implicit $exec
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%63:vgpr_32, %65:sreg_64_xexec = V_ADD_CO_U32_e64 %30.sub0, %23, 0, implicit $exec
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$vcc = COPY %30
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%31:vreg_64 = COPY killed $vcc
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%64:vgpr_32, %66:sreg_64_xexec = V_ADDC_U32_e64 %30.sub1, %0, %65, 0, implicit $exec
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%62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
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GLOBAL_STORE_DWORDX2_SADDR %31.sub0, %62, %1, 0, 0, 0, 0, implicit $exec, implicit $exec :: (store 8)
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