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0487d18102
This patch adds assembler support for the remaining branch instructions: the non-relative branch on count variants, and all variants of branch on index. The only one of those that can be readily exploited for code generation is BRCTH (branch on count using a high 32-bit register as count). Do use it, however, it is necessary to also introduce a hew CHIMux pseudo to allow comparisons of a 32-bit value agains a short immediate to go into a high register as well (implemented via CHI/CIH). This causes a bit of codegen changes overall, but those have proven to be neutral (or even beneficial) in performance measurements. llvm-svn: 288029
39 lines
1016 B
LLVM
39 lines
1016 B
LLVM
; Test BRCTH.
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; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z196 \
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; RUN: -no-integrated-as | FileCheck %s
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; Test a loop that should be converted into dbr form and then use BRCTH.
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define void @f2(i32 *%src, i32 *%dest) {
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; CHECK-LABEL: f2:
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; CHECK: blah [[REG:%r[0-5]]]
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; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
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; CHECK: brcth [[REG]], [[LABEL]]
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; CHECK: br %r14
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entry:
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; Force upper bound into a high register in order to encourage the
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; register allocator to use a high register for the count variable.
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%top = call i32 asm sideeffect "blah $0", "=h"()
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br label %loop
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loop:
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%count = phi i32 [ 0, %entry ], [ %next, %loop.next ]
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%next = add i32 %count, 1
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%val = load volatile i32 , i32 *%src
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %loop.next, label %loop.store
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loop.store:
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%add = add i32 %val, 1
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store volatile i32 %add, i32 *%dest
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br label %loop.next
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loop.next:
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%cont = icmp ne i32 %next, %top
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br i1 %cont, label %loop, label %exit
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exit:
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ret void
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}
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