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6c7366f926
Summary: This enables further transforms. Depends on D32916 Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32925 llvm-svn: 304401
41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
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; These tests use adc/sbb in place of set+add/sub. Should this transform
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; be enabled by micro-architecture rather than as part of generic lowering/isel?
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; <rdar://problem/8449754>
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define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: adcl %ecx, %eax
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; CHECK-NEXT: retl
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%add4 = add i32 %x, %sum
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%cmp = icmp ult i32 %add4, %x
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%inc = zext i1 %cmp to i32
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%z.0 = add i32 %add4, %inc
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ret i32 %z.0
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}
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; <rdar://problem/12579915>
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define i32 @test2(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: sbbl $0, %eax
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; CHECK-NEXT: retl
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%cmp = icmp ugt i32 %x, %y
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%dec = sext i1 %cmp to i32
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%dec.res = add nsw i32 %dec, %res
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ret i32 %dec.res
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}
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