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12eb12a774
The dream of a unified check-line auto-generator for all phases of compilation is dead. The llc script has already diverged to be better at its goal, so having 2 scripts that do almost the same thing is just causing confusion. We can rip out the llc ability in update_test_checks.py next and rename it, so it will be clear that we have one script for llc check auto-generation and another for opt. llvm-svn: 305206
81 lines
2.1 KiB
LLVM
81 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
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define i32 @test1(i32 %X) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: imull %edx
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; CHECK-NEXT: addl %ecx, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shrl $31, %eax
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; CHECK-NEXT: sarl $7, %edx
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; CHECK-NEXT: addl %eax, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: subl %eax, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = srem i32 %X, 255
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ret i32 %tmp1
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}
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define i32 @test2(i32 %X) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: sarl $31, %ecx
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; CHECK-NEXT: shrl $24, %ecx
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; CHECK-NEXT: addl %eax, %ecx
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; CHECK-NEXT: andl $-256, %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = srem i32 %X, 256
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ret i32 %tmp1
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}
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define i32 @test3(i32 %X) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl $-2139062143, %edx # imm = 0x80808081
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: mull %edx
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; CHECK-NEXT: shrl $7, %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: shll $8, %eax
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; CHECK-NEXT: subl %edx, %eax
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; CHECK-NEXT: subl %eax, %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%tmp1 = urem i32 %X, 255
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ret i32 %tmp1
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}
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define i32 @test4(i32 %X) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%tmp1 = urem i32 %X, 256
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ret i32 %tmp1
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}
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define i32 @test5(i32 %X) nounwind readnone {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: idivl {{[0-9]+}}(%esp)
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retl
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entry:
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%0 = srem i32 41, %X
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ret i32 %0
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}
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