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8fe52dcc51
This is a follow-up from D38181 (r314023). We have to put 64-bit constants into a register using a separate instruction, so we should try harder to avoid that. From what I see, we're not likely to encounter this pattern in the DAG because the upstream setcc combines from this don't (usually?) produce this pattern. If we fix that, then this will become more relevant. Since the cost of handling this case is just loosening the predicate of the existing fold, we might as well do it now. llvm-svn: 314064
217 lines
5.5 KiB
LLVM
217 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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define i32 @t1(i32 %t, i32 %val) nounwind {
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; X32-LABEL: t1:
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; X32: # BB#0:
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: shll %cl, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t1:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: shll %cl, %esi
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: retq
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%shamt = and i32 %t, 31
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%res = shl i32 %val, %shamt
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ret i32 %res
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}
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define i32 @t2(i32 %t, i32 %val) nounwind {
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; X32-LABEL: t2:
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; X32: # BB#0:
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: shll %cl, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t2:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: shll %cl, %esi
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: retq
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%shamt = and i32 %t, 63
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%res = shl i32 %val, %shamt
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ret i32 %res
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}
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@X = internal global i16 0
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define void @t3(i16 %t) nounwind {
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; X32-LABEL: t3:
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; X32: # BB#0:
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: sarw %cl, X
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; X32-NEXT: retl
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;
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; X64-LABEL: t3:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: sarw %cl, {{.*}}(%rip)
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; X64-NEXT: retq
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%shamt = and i16 %t, 31
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%tmp = load i16, i16* @X
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%tmp1 = ashr i16 %tmp, %shamt
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store i16 %tmp1, i16* @X
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ret void
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}
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define i64 @t4(i64 %t, i64 %val) nounwind {
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; X32-LABEL: t4:
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; X32: # BB#0:
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; X32-NEXT: pushl %esi
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, %edx
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; X32-NEXT: shrl %cl, %edx
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; X32-NEXT: shrdl %cl, %esi, %eax
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; X32-NEXT: testb $32, %cl
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; X32-NEXT: je .LBB3_2
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; X32-NEXT: # BB#1:
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; X32-NEXT: movl %edx, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: .LBB3_2:
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; X32-NEXT: popl %esi
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; X32-NEXT: retl
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;
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; X64-LABEL: t4:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: shrq %cl, %rsi
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; X64-NEXT: movq %rsi, %rax
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; X64-NEXT: retq
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%shamt = and i64 %t, 63
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%res = lshr i64 %val, %shamt
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ret i64 %res
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}
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define i64 @t5(i64 %t, i64 %val) nounwind {
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; X32-LABEL: t5:
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; X32: # BB#0:
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; X32-NEXT: pushl %esi
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl %esi, %edx
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; X32-NEXT: shrl %cl, %edx
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; X32-NEXT: shrdl %cl, %esi, %eax
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; X32-NEXT: testb $32, %cl
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; X32-NEXT: je .LBB4_2
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; X32-NEXT: # BB#1:
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; X32-NEXT: movl %edx, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: .LBB4_2:
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; X32-NEXT: popl %esi
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; X32-NEXT: retl
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;
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; X64-LABEL: t5:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: shrq %cl, %rsi
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; X64-NEXT: movq %rsi, %rax
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; X64-NEXT: retq
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%shamt = and i64 %t, 191
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%res = lshr i64 %val, %shamt
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ret i64 %res
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}
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define void @t5ptr(i64 %t, i64* %ptr) nounwind {
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; X32-LABEL: t5ptr:
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; X32: # BB#0:
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl (%eax), %edx
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; X32-NEXT: movl 4(%eax), %edi
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; X32-NEXT: movl %edi, %esi
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; X32-NEXT: shrl %cl, %esi
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; X32-NEXT: shrdl %cl, %edi, %edx
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; X32-NEXT: testb $32, %cl
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; X32-NEXT: je .LBB5_2
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; X32-NEXT: # BB#1:
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; X32-NEXT: movl %esi, %edx
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; X32-NEXT: xorl %esi, %esi
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; X32-NEXT: .LBB5_2:
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; X32-NEXT: movl %esi, 4(%eax)
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; X32-NEXT: movl %edx, (%eax)
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: retl
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;
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; X64-LABEL: t5ptr:
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; X64: # BB#0:
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; X64-NEXT: movl %edi, %ecx
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; X64-NEXT: shrq %cl, (%rsi)
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; X64-NEXT: retq
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%shamt = and i64 %t, 191
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%tmp = load i64, i64* %ptr
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%tmp1 = lshr i64 %tmp, %shamt
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store i64 %tmp1, i64* %ptr
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ret void
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}
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; rdar://11866926
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define i64 @t6(i64 %key, i64* nocapture %val) nounwind {
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; X32-LABEL: t6:
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; X32: # BB#0:
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: shrdl $3, %eax, %esi
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; X32-NEXT: movl %eax, %edi
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; X32-NEXT: shrl $3, %edi
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; X32-NEXT: movl (%ecx), %eax
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; X32-NEXT: movl 4(%ecx), %edx
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; X32-NEXT: addl $-1, %eax
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; X32-NEXT: adcl $-1, %edx
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; X32-NEXT: andl %esi, %eax
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; X32-NEXT: andl %edi, %edx
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: retl
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;
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; X64-LABEL: t6:
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; X64: # BB#0:
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; X64-NEXT: shrq $3, %rdi
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; X64-NEXT: movq (%rsi), %rax
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; X64-NEXT: decq %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: retq
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%shr = lshr i64 %key, 3
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%1 = load i64, i64* %val, align 8
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%sub = add i64 %1, 2305843009213693951
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%and = and i64 %sub, %shr
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ret i64 %and
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}
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define i64 @big_mask_constant(i64 %x) nounwind {
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; X32-LABEL: big_mask_constant:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $4, %eax
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; X32-NEXT: shll $25, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: retl
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;
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; X64-LABEL: big_mask_constant:
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; X64: # BB#0:
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; X64-NEXT: shrq $7, %rdi
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; X64-NEXT: andl $134217728, %edi # imm = 0x8000000
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: retq
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%and = and i64 %x, 17179869184 ; 0x400000000
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%sh = lshr i64 %and, 7
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ret i64 %sh
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}
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