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43a91b22c0
Convert vector increment or decrement to sub/add with an all-ones constant: add X, <1, 1...> --> sub X, <-1, -1...> sub X, <1, 1...> --> add X, <-1, -1...> The all-ones vector constant can be materialized using a pcmpeq instruction that is commonly recognized as an idiom (has no register dependency), so that's better than loading a splat 1 constant. AVX512 uses 'vpternlogd' for 512-bit vectors because there is apparently no better way to produce 512 one-bits. The general advantages of this lowering are: 1. pcmpeq has lower latency than a memop on every uarch I looked at in Agner's tables, so in theory, this could be better for perf, but... 2. That seems unlikely to affect any OOO implementation, and I can't measure any real perf difference from this transform on Haswell or Jaguar, but... 3. It doesn't look like it from the diffs, but this is an overall size win because we eliminate 16 - 64 constant bytes in the case of a vector load. If we're broadcasting a scalar load (which might itself be a bug), then we're replacing a scalar constant load + broadcast with a single cheap op, so that should always be smaller/better too. 4. This makes the DAG/isel output more consistent - we use pcmpeq already for padd x, -1 and psub x, -1, so we should use that form for +1 too because we can. If there's some reason to favor a constant load on some CPU, let's make the reverse transform for all of these cases (either here in the DAG or in a later machine pass). This should fix: https://bugs.llvm.org/show_bug.cgi?id=33483 Differential Revision: https://reviews.llvm.org/D34336 llvm-svn: 306289
71 lines
2.3 KiB
LLVM
71 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.2 | FileCheck %s
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define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind {
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; CHECK-LABEL: update:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: subl $12, %esp
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; CHECK-NEXT: movl $0, (%esp)
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; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
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; CHECK-NEXT: jmp .LBB0_1
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_2: # %forbody
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; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: movl (%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: pmovzxbd {{.*#+}} xmm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; CHECK-NEXT: psubd %xmm0, %xmm2
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; CHECK-NEXT: pextrb $8, %xmm2, 2(%ecx,%eax,4)
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; CHECK-NEXT: pshufb %xmm1, %xmm2
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; CHECK-NEXT: pextrw $0, %xmm2, (%ecx,%eax,4)
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; CHECK-NEXT: incl (%esp)
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; CHECK-NEXT: .LBB0_1: # %forcond
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movl (%esp), %eax
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: jl .LBB0_2
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; CHECK-NEXT: # BB#3: # %afterfor
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; CHECK-NEXT: addl $12, %esp
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; CHECK-NEXT: retl
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entry:
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%dst.addr = alloca <3 x i8>*
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%src.addr = alloca <3 x i8>*
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%n.addr = alloca i32
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%i = alloca i32, align 4
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store <3 x i8>* %dst, <3 x i8>** %dst.addr
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store <3 x i8>* %src, <3 x i8>** %src.addr
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store i32 %n, i32* %n.addr
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store i32 0, i32* %i
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br label %forcond
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forcond:
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%tmp = load i32, i32* %i
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%tmp1 = load i32, i32* %n.addr
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%cmp = icmp slt i32 %tmp, %tmp1
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br i1 %cmp, label %forbody, label %afterfor
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forbody:
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%tmp2 = load i32, i32* %i
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%tmp3 = load <3 x i8>*, <3 x i8>** %dst.addr
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%arrayidx = getelementptr <3 x i8>, <3 x i8>* %tmp3, i32 %tmp2
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%tmp4 = load i32, i32* %i
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%tmp5 = load <3 x i8>*, <3 x i8>** %src.addr
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%arrayidx6 = getelementptr <3 x i8>, <3 x i8>* %tmp5, i32 %tmp4
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%tmp7 = load <3 x i8>, <3 x i8>* %arrayidx6
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%add = add <3 x i8> %tmp7, < i8 1, i8 1, i8 1 >
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store <3 x i8> %add, <3 x i8>* %arrayidx
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br label %forinc
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forinc:
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%tmp8 = load i32, i32* %i
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%inc = add i32 %tmp8, 1
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store i32 %inc, i32* %i
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br label %forcond
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afterfor:
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ret void
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}
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