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d9c22f7404
LowerBuildVectorv16i8/LowerBuildVectorv8i16 insert values into a UNDEF vector if the build vector doesn't contain any zero elements, resulting in register dependencies with a previous use of the register. This patch attempts to break the register dependency by either always zeroing the vector before hand or (if we're inserting to the 0'th element) by using VZEXT_MOVL(SCALAR_TO_VECTOR(i32 AEXT(Elt))) which lowers to (V)MOVD and performs a similar function. Additionally (V)MOVD is a shorter instruction than PINSRB/PINSRW. We already do something similar for SSE41 PINSRD. On pre-SSE41 LowerBuildVectorv16i8 we go a little further and use VZEXT_MOVL(SCALAR_TO_VECTOR(i32 ZEXT(Elt))) if the build vector contains zeros to avoid the vector zeroing at the cost of a scalar zero extension, which can probably be brought over to the other cases in a future patch in some cases (load folding etc.) Differential Revision: https://reviews.llvm.org/D29720 llvm-svn: 294581
308 lines
9.6 KiB
LLVM
308 lines
9.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42
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;
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; AND/XOR/OR i24 as v3i8
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;
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define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: and_i24_as_v3i8:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: and_i24_as_v3i8:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: andl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <3 x i8>
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%2 = bitcast i24 %b to <3 x i8>
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%3 = and <3 x i8> %1, %2
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%4 = bitcast <3 x i8> %3 to i24
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ret i24 %4
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}
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define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: xor_i24_as_v3i8:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: xor_i24_as_v3i8:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: xorl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <3 x i8>
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%2 = bitcast i24 %b to <3 x i8>
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%3 = xor <3 x i8> %1, %2
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%4 = bitcast <3 x i8> %3 to i24
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ret i24 %4
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}
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define i24 @or_i24_as_v3i8(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: or_i24_as_v3i8:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: or_i24_as_v3i8:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: orl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <3 x i8>
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%2 = bitcast i24 %b to <3 x i8>
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%3 = or <3 x i8> %1, %2
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%4 = bitcast <3 x i8> %3 to i24
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ret i24 %4
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}
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;
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; AND/XOR/OR i24 as v8i3
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;
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define i24 @and_i24_as_v8i3(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: and_i24_as_v8i3:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: and_i24_as_v8i3:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: andl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <8 x i3>
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%2 = bitcast i24 %b to <8 x i3>
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%3 = and <8 x i3> %1, %2
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%4 = bitcast <8 x i3> %3 to i24
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ret i24 %4
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}
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define i24 @xor_i24_as_v8i3(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: xor_i24_as_v8i3:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: xor_i24_as_v8i3:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: xorl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <8 x i3>
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%2 = bitcast i24 %b to <8 x i3>
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%3 = xor <8 x i3> %1, %2
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%4 = bitcast <8 x i3> %3 to i24
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ret i24 %4
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}
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define i24 @or_i24_as_v8i3(i24 %a, i24 %b) nounwind {
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; X32-SSE-LABEL: or_i24_as_v8i3:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: or_i24_as_v8i3:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: orl %esi, %edi
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; X64-SSE-NEXT: movl %edi, %eax
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; X64-SSE-NEXT: retq
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%1 = bitcast i24 %a to <8 x i3>
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%2 = bitcast i24 %b to <8 x i3>
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%3 = or <8 x i3> %1, %2
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%4 = bitcast <8 x i3> %3 to i24
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ret i24 %4
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}
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;
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; AND/XOR/OR v3i8 as i24
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;
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define <3 x i8> @and_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
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; X32-SSE-LABEL: and_v3i8_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: pand %xmm0, %xmm1
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; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: and_v3i8_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: movd %ecx, %xmm0
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; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
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; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
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; X64-SSE-NEXT: movd %edi, %xmm1
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; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
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; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
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; X64-SSE-NEXT: pand %xmm0, %xmm1
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; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X64-SSE-NEXT: retq
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%1 = bitcast <3 x i8> %a to i24
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%2 = bitcast <3 x i8> %b to i24
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%3 = and i24 %1, %2
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%4 = bitcast i24 %3 to <3 x i8>
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ret <3 x i8> %4
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}
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define <3 x i8> @xor_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
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; X32-SSE-LABEL: xor_v3i8_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: pxor %xmm0, %xmm1
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; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: xor_v3i8_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: movd %ecx, %xmm0
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; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
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; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
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; X64-SSE-NEXT: movd %edi, %xmm1
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; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
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; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
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; X64-SSE-NEXT: pxor %xmm0, %xmm1
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; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X64-SSE-NEXT: retq
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%1 = bitcast <3 x i8> %a to i24
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%2 = bitcast <3 x i8> %b to i24
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%3 = xor i24 %1, %2
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%4 = bitcast i24 %3 to <3 x i8>
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ret <3 x i8> %4
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}
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define <3 x i8> @or_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
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; X32-SSE-LABEL: or_v3i8_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
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; X32-SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
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; X32-SSE-NEXT: por %xmm0, %xmm1
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; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X32-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X32-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X32-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: or_v3i8_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: movd %ecx, %xmm0
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; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
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; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
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; X64-SSE-NEXT: movd %edi, %xmm1
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; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
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; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
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; X64-SSE-NEXT: por %xmm0, %xmm1
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; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
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; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
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; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
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; X64-SSE-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
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; X64-SSE-NEXT: # kill: %DL<def> %DL<kill> %EDX<kill>
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; X64-SSE-NEXT: # kill: %CL<def> %CL<kill> %ECX<kill>
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; X64-SSE-NEXT: retq
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%1 = bitcast <3 x i8> %a to i24
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%2 = bitcast <3 x i8> %b to i24
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%3 = or i24 %1, %2
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%4 = bitcast i24 %3 to <3 x i8>
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ret <3 x i8> %4
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}
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;
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; AND/XOR/OR v8i3 as i24
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;
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define <8 x i3> @and_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
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; X32-SSE-LABEL: and_v8i3_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: andps %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: and_v8i3_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: andps %xmm1, %xmm0
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; X64-SSE-NEXT: retq
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%1 = bitcast <8 x i3> %a to i24
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%2 = bitcast <8 x i3> %b to i24
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%3 = and i24 %1, %2
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%4 = bitcast i24 %3 to <8 x i3>
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ret <8 x i3> %4
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}
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define <8 x i3> @xor_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
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; X32-SSE-LABEL: xor_v8i3_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: xorps %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: xor_v8i3_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: xorps %xmm1, %xmm0
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; X64-SSE-NEXT: retq
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%1 = bitcast <8 x i3> %a to i24
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%2 = bitcast <8 x i3> %b to i24
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%3 = xor i24 %1, %2
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%4 = bitcast i24 %3 to <8 x i3>
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ret <8 x i3> %4
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}
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define <8 x i3> @or_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
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; X32-SSE-LABEL: or_v8i3_as_i24:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: orps %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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;
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; X64-SSE-LABEL: or_v8i3_as_i24:
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; X64-SSE: # BB#0:
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; X64-SSE-NEXT: orps %xmm1, %xmm0
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; X64-SSE-NEXT: retq
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%1 = bitcast <8 x i3> %a to i24
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%2 = bitcast <8 x i3> %b to i24
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%3 = or i24 %1, %2
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%4 = bitcast i24 %3 to <8 x i3>
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ret <8 x i3> %4
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}
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