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llvm-mirror/test/CodeGen
Nirav Dave 7b6e012d2f Fix Load Control Dependence in MemCpy Generation
In Memcpy lowering we had missed a dependence from the load of the
operation to successor operations. This causes us to potentially
construct an in initial DAG with a memory dependence not fully
represented in the chain sub-DAG but rather require looking at the
entire DAG breaking alias analysis by allowing incorrect repositioning
of memory operations.

To work around this, r200033 changed DAGCombiner::GatherAllAliases to be
conservative if any possible issues to happen. Unfortunately this check
forbade many non-problematic situations as well. For example, it's
common for incoming argument lowering to add a non-aliasing load hanging
off of EntryNode. Then, if GatherAllAliases visited EntryNode, it would
find that other (unvisited) use of the EntryNode chain, and just give up
entirely. Furthermore, the check was incomplete: it would not actually
detect all such potentially problematic DAG constructions, because
GatherAllAliases did not guarantee to visit all chain nodes going up to
the root EntryNode. This is in general fine -- giving up early will just
miss a potential optimization, not generate incorrect results. But, for
this non-chain dependency detection code, it's possible that you could
have a load attached to a higher-up chain node than any which were
visited. If that load aliases your store, but the only dependency is
through the value operand of a non-aliasing store, it would've been
missed by this code, and potentially reordered.

With the dependence added, this check can be removed and Alias Analysis
can be much more aggressive. This fixes code quality regression in the
Consecutive Store Merge cleanup (D14834).

Test Change:

ppc64-align-long-double.ll now may see multiple serializations
of its stores

Differential Revision: http://reviews.llvm.org/D18062

llvm-svn: 265836
2016-04-08 19:44:40 +00:00
..
AArch64 [AArch64] Add a test case for the default mapping of RegBankSelect. 2016-04-08 17:11:51 +00:00
AMDGPU AMDGPU/SI: Implement atomic load/store for i32 and i64 2016-04-07 19:23:11 +00:00
ARM Revert r265817 2016-04-08 18:15:37 +00:00
BPF
CPP
Generic Add missing test for the "Don't delete empty preheaders" added in r265397 2016-04-05 14:21:32 +00:00
Hexagon Revert r265817 2016-04-08 18:15:37 +00:00
Inputs
Lanai [lanai] LanaiSetflagAluCombiner more conservative 2016-04-05 16:18:13 +00:00
Mips Revert r265817 2016-04-08 18:15:37 +00:00
MIR [MIR] Teach the parser how to deal with register banks. 2016-04-08 16:40:43 +00:00
MSP430
NVPTX [NVPTX] Handle ldg created from sign-/zero-extended load 2016-04-05 12:38:01 +00:00
PowerPC Fix Load Control Dependence in MemCpy Generation 2016-04-08 19:44:40 +00:00
SPARC
SystemZ [SystemZ] Support conditional sibling calls via BRCL 2016-04-08 17:22:19 +00:00
Thumb Revert r265817 2016-04-08 18:15:37 +00:00
Thumb2
WebAssembly WebAssembly: fix cfg-stackify test 2016-04-05 17:01:52 +00:00
WinEH
X86 [X86] Fix PR23155 by turning on X86FixupBWInsts by default. 2016-04-08 18:58:29 +00:00
XCore