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In debug frame information, some fields, e.g., Length in CIE/FDE and Offset in FDE are attributes to describe the structure of CIE/FDE. They are not related to the relaxed code. However, these attributes are symbol differences. So, in current design, these attributes will be filled as zero and LLVM generates relocations for them. We only need to generate relocations for symbols in executable sections. So, if the symbols are not located in executable sections, we still evaluate their values under relaxation. Differential Revision: https://reviews.llvm.org/D61584 llvm-svn: 366531
29 lines
1.1 KiB
ArmAsm
29 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
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# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
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# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX-RELOC %s
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func:
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.cfi_startproc
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ret
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.cfi_endproc
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# TODO: Should produce R_RISCV_32_PCREL for the FDE pc relocation. Many of the
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# ADD32/SUB32 relocations also can be safely resolved even with linker
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# relaxation enabled. This test is written to capture current behaviour, in
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# preparation for follow-on patches to fix it.
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# RELAX-RELOC: Section (4) .rela.eh_frame {
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# RELAX-RELOC-NEXT: 0x0 R_RISCV_32 - 0x10
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# RELAX-RELOC-NEXT: 0x14 R_RISCV_32 - 0x10
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# RELAX-RELOC-NEXT: 0x18 R_RISCV_32 - 0x18
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# RELAX-RELOC-NEXT: 0x1C R_RISCV_ADD32 - 0x0
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# RELAX-RELOC-NEXT: 0x1C R_RISCV_SUB32 - 0x0
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# RELAX-RELOC-NEXT: 0x20 R_RISCV_ADD32 - 0x0
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# RELAX-RELOC-NEXT: 0x20 R_RISCV_SUB32 - 0x0
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# RELAX-RELOC-NEXT: }
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# NORELAX-RELOC: Section (4) .rela.eh_frame {
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# NORELAX-RELOC-NEXT: 0x1C R_RISCV_32_PCREL - 0x0
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# NORELAX-RELOC-NEXT: }
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