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1eacb83316
register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
46 lines
1.3 KiB
LLVM
46 lines
1.3 KiB
LLVM
; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o -
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; When a i64 sub is expanded to subc + sube.
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; libcall #1
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; \
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; \ subc
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; \ / \
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; \ / \
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; \ / libcall #2
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; sube
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;
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; If the libcalls are not serialized (i.e. both have chains which are dag
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; entry), legalizer can serialize them in arbitrary orders. If it's
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; unlucky, it can force libcall #2 before libcall #1 in the above case.
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;
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; subc
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; |
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; libcall #2
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; |
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; libcall #1
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; |
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; sube
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;
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; However since subc and sube are "glued" together, this ends up being a
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; cycle when the scheduler combine subc and sube as a single scheduling
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; unit.
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;
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; The right solution is to fix LegalizeType too chains the libcalls together.
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; However, LegalizeType is not processing nodes in order. The fix now is to
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; fix subc / sube (and addc / adde) to use physical register dependency instead.
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; rdar://10019576
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define void @t() nounwind {
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entry:
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%tmp = load i64* undef, align 4
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%tmp5 = udiv i64 %tmp, 30
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%tmp13 = and i64 %tmp5, 64739244643450880
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%tmp16 = sub i64 0, %tmp13
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%tmp19 = and i64 %tmp16, 63
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%tmp20 = urem i64 %tmp19, 3
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%tmp22 = and i64 %tmp16, -272346829004752
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store i64 %tmp22, i64* undef, align 4
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store i64 %tmp20, i64* undef, align 4
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ret void
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}
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