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adb91e7ed9
Introduction: In case when stack alignment is 8 and GPRs parameter part size is not N*8: we add padding to GPRs part, so part's last byte must be recovered at address K*8-1. We need to do it, since remained (stack) part of parameter starts from address K*8, and we need to "attach" "GPRs head" without gaps to it: Stack: |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes... [ [padding] [GPRs head] ] [ ------ Tail passed via stack ------ ... FIX: Note, once we added padding we need to correct *all* Arg offsets that are going after padded one. That's why we need this fix: Arg offsets were never corrected before this patch. See new test-cases included in patch. We also don't need to insert padding for byval parameters that are stored in GPRs only. We need pad only last byval parameter and only in case it outsides GPRs and stack alignment = 8. Though, stack area, allocated for recovered byval params, must satisfy "Size mod 8 = 0" restriction. This patch reduces stack usage for some cases: We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be "packed" with alignment 4 in some cases. llvm-svn: 182237
32 lines
769 B
LLVM
32 lines
769 B
LLVM
;PR15293: ARM codegen ice - expected larger existing stack allocation
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;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
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%struct.S227 = type { [49 x i32], i32 }
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define void @check227(
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i32 %b,
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%struct.S227* byval nocapture %arg0,
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%struct.S227* %arg1) {
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; b --> R0
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; arg0 --> [R1, R2, R3, SP+0 .. SP+188)
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; arg1 --> SP+188
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entry:
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;CHECK: sub sp, sp, #16
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;CHECK: push {r11, lr}
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;CHECK: add r0, sp, #12
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;CHECK: stm r0, {r1, r2, r3}
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;CHECK: ldr r0, [sp, #212]
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;CHECK: bl useInt
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;CHECK: pop {r11, lr}
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;CHECK: add sp, sp, #16
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%0 = ptrtoint %struct.S227* %arg1 to i32
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tail call void @useInt(i32 %0)
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ret void
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}
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declare void @useInt(i32)
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