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7bdfbd6570
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled because it relied on broken EXTSW_32/STD_32 instruction definitions. The original intent had been to enable these 64-bit instructions to be used on CPUs that support them even in 32-bit mode. Unfortunately, this form of lying to the infrastructure was buggy (as explained in the FIXME comment) and had therefore been disabled. This re-enables this functionality, using regular DAG nodes, but only when compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead) are removed. llvm-svn: 178438
32 lines
763 B
LLVM
32 lines
763 B
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define float @foo(i32 %a) nounwind {
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entry:
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%x = sitofp i32 %a to float
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ret float %x
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; CHECK: @foo
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; CHECK: extsw [[REG:[0-9]+]], 3
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; CHECK: std [[REG]],
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; CHECK: lfd [[REG2:[0-9]+]],
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; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]
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; CHECK: frsp 1, [[REG3]]
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; CHECK: blr
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}
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define double @goo(i32 %a) nounwind {
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entry:
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%x = sitofp i32 %a to double
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ret double %x
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; CHECK: @goo
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; CHECK: extsw [[REG:[0-9]+]], 3
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; CHECK: std [[REG]],
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; CHECK: lfd [[REG2:[0-9]+]],
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; CHECK: fcfid 1, [[REG2]]
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; CHECK: blr
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}
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