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fb2c0a0ef7
This was happening because the BLR didn't have a use of the X0 arg register, which would end up being re-used in high reg pressure situations. The change also avoids hard coding the use of X0 for the sequence except to copy the value for the call. ld64 should still be able to optimize it. rdar://65438258
20 lines
705 B
LLVM
20 lines
705 B
LLVM
; RUN: llc -mtriple=arm64-apple-ios7.0 %s -o - | FileCheck %s
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; RUN: llc -mtriple=arm64-apple-ios7.0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
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@var = thread_local global i8 0
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; N.b. x0 must be the result of the first load (i.e. the address of the
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; descriptor) when tlv_get_addr is called. Likewise the result is returned in
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; x0.
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define i8 @get_var() {
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; CHECK-LABEL: get_var:
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; CHECK: adrp x[[TLVPDESC_SLOT_HI:[0-9]+]], _var@TLVPPAGE
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; CHECK: ldr x[[PTR:[0-9]+]], [x[[TLVPDESC_SLOT_HI]], _var@TLVPPAGEOFF]
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; CHECK: ldr [[TLV_GET_ADDR:x[0-9]+]], [x[[PTR]]]
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; CHECK: blr [[TLV_GET_ADDR]]
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; CHECK: ldrb w0, [x0]
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%val = load i8, i8* @var, align 1
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ret i8 %val
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}
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