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c4f084e133
In cases where MachineOutliner candidates either are:
* noreturn
* have calls with no available LR or free regs
* Don't use SP
we can end up hitting stack fixup code for the caller and the callee for
a FrameID of MachineOutlinerDefault. This triggers the assert:
`assert(OF.FrameConstructionID != MachineOutlinerDefault &&
"Can only fix up stack references once");`
in AArch64InstrInfo.cpp. This assert exists for now because a lot of the
fixup code is not tested to handle fixing up more than once and needs
some better checks and enhancements to avoid potentially generating
illegal code.
I've filed a Bugzilla report to track this until these cases are handled
by the AArch64 MachineOutliner: https://bugs.llvm.org/show_bug.cgi?id=46767
This diff detects cases that will cause these multiple stack fixups and
prune the Candidates from `RepeatedSequenceLocs`.
Differential Revision: https://reviews.llvm.org/D83923
76 lines
2.6 KiB
YAML
76 lines
2.6 KiB
YAML
# RUN: llc -mtriple=aarch64--- -run-pass=machine-outliner \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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# CHECK-NOT: OUTLINED_FUNCTION
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--- |
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define void @f1() #0 { ret void }
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define void @f2() #0 { ret void }
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define void @f3() #0 { ret void }
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define void @f4() #0 { ret void }
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attributes #0 = { minsize noredzone "branch-target-enforcement" }
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...
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---
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name: f1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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$x20, $x19 = LDPXi $sp, 11
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$x20, $x19 = LDPXi $sp, 12
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$x20, $x19 = LDPXi $sp, 13
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$x20, $x19 = LDPXi $sp, 14
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$x20, $x19 = LDPXi $sp, 18
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$x20, $x19 = LDPXi $sp, 19
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$x20, $x19 = LDPXi $sp, 20
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$x20, $x19 = LDPXi $sp, 21
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BLR $x20, implicit $sp
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bb.2:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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RET undef $lr
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...
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---
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name: f2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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$x20, $x19 = LDPXi $sp, 11
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$x20, $x19 = LDPXi $sp, 12
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$x20, $x19 = LDPXi $sp, 13
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$x20, $x19 = LDPXi $sp, 14
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$x20, $x19 = LDPXi $sp, 18
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$x20, $x19 = LDPXi $sp, 19
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$x20, $x19 = LDPXi $sp, 20
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$x20, $x19 = LDPXi $sp, 21
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BLR $x20, implicit $sp
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bb.2:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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RET undef $lr
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...
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---
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name: f3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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$x20, $x19 = LDPXi $sp, 11
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$x20, $x19 = LDPXi $sp, 12
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$x20, $x19 = LDPXi $sp, 13
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$x20, $x19 = LDPXi $sp, 14
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$x20, $x19 = LDPXi $sp, 18
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$x20, $x19 = LDPXi $sp, 19
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$x20, $x19 = LDPXi $sp, 20
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$x20, $x19 = LDPXi $sp, 21
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BLR $x20, implicit $sp
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bb.2:
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liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x18, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $fp
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RET undef $lr
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...
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---
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name: f4
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tracksRegLiveness: true
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body: |
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bb.0:
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RET undef $lr
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