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llvm-mirror/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
James Y Knight af0734bc33 Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.
Before this instruction supported output values, it fit fairly
naturally as a terminator. However, being a terminator while also
supporting outputs causes some trouble, as the physreg->vreg COPY
operations cannot be in the same block.

Modeling it as a non-terminator allows it to be handled the same way
as invoke is handled already.

Most of the changes here were created by auditing all the existing
users of MachineBasicBlock::isEHPad() and
MachineBasicBlock::hasEHPadSuccessor(), and adding calls to
isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate.

Reviewed By: nickdesaulniers, void

Differential Revision: https://reviews.llvm.org/D79794
2020-07-01 12:51:50 -04:00

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2.8 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -run-pass=if-converter -verify-machineinstrs | FileCheck %s
# Make sure we correctly if-convert blocks containing an unanalyzable branch sequence.
# (In this case, multiple conditional branches)
--- |
target triple = "thumbv7-unknown-linux-gnueabi"
define dso_local void @fn1() {
l_yes:
ret void
}
declare dso_local i32 @fn2(...)
...
---
name: fn1
alignment: 2
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: fn1
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $r0, $r1, $r2, $r4, $lr
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $lr
; CHECK: t2CMPri killed renamable $r2, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
; CHECK: $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
; CHECK: tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
; CHECK: t2CMPri $sp, 34, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.2, 1 /* CC::ne */, $cpsr
; CHECK: t2Bcc %bb.2, 2 /* CC::hs */, killed $cpsr
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
; CHECK: INLINEASM &"", 1
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.2.l_yes (address-taken):
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $r0, $r1, $r2, $r4, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
t2CMPri killed renamable $r2, 34, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 1, killed $cpsr
bb.1:
successors: %bb.3(0x40000000), %bb.4(0x40000000)
liveins: $r1
$r0 = t2MOVi 3, 14, $noreg, $noreg
tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
t2CMPri $sp, 34, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.4, 1, $cpsr
t2Bcc %bb.4, 2, killed $cpsr
t2B %bb.3, 14, $noreg
bb.2:
successors: %bb.3(0x40000000), %bb.4(0x40000000)
liveins: $r1
$r0 = t2MOVi 2, 14, $noreg, $noreg
tBL 14, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
t2CMPri $sp, 34, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.4, 1, $cpsr
t2Bcc %bb.4, 2, killed $cpsr
t2B %bb.3, 14, $noreg
bb.3:
INLINEASM &"", 1
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
bb.4.l_yes (address-taken):
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
...