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llvm-mirror/test/CodeGen/ARM/ipra-no-csr.ll
Oliver Stannard fac519c9d7 [IPRA][ARM] Disable no-CSR optimisation for ARM
This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.

Differential revision: https://reviews.llvm.org/D64910

llvm-svn: 367670
2019-08-02 10:23:17 +00:00

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631 B
LLVM

; RUN: llc -mtriple armv7a--none-eabi < %s | FileCheck %s
; RUN: llc -mtriple armv7a--none-eabi < %s -enable-ipra | FileCheck %s
; Other targets disable callee-saved registers for internal functions when
; using IPRA, but that isn't profitable for ARM because the PUSH/POP
; instructions can more efficiently save registers than using individual
; LDR/STRs in the caller.
define internal void @callee() norecurse {
; CHECK-LABEL: callee:
entry:
; CHECK: push {r4, lr}
; CHECK: pop {r4, pc}
tail call void asm sideeffect "", "~{r4}"()
ret void
}
define void @caller() {
entry:
call void @callee()
ret void
}