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Differential revision: https://reviews.llvm.org/D72701 The patch adds a new option ABI for Hexagon. It primary deals with the way variable arguments are passed and is use in the Hexagon Linux Musl environment. If a callee function has a variable argument list, it must perform the following operations to set up its function prologue: 1. Determine the number of registers which could have been used for passing unnamed arguments. This can be calculated by counting the number of registers used for passing named arguments. For example, if the callee function is as follows: int foo(int a, ...){ ... } ... then register R0 is used to access the argument ' a '. The registers available for passing unnamed arguments are R1, R2, R3, R4, and R5. 2. Determine the number and size of the named arguments on the stack. 3. If the callee has named arguments on the stack, it should copy all of these arguments to a location below the current position on the stack, and the difference should be the size of the register-saved area plus padding (if any is necessary). The register-saved area constitutes all the registers that could have been used to pass unnamed arguments. If the number of registers forming the register-saved area is odd, it requires 4 bytes of padding; if the number is even, no padding is required. This is done to ensure an 8-byte alignment on the stack. For example, if the callee is as follows: int foo(int a, ...){ ... } ... then the named arguments should be copied to the following location: current_position - 5 (for R1-R5) * 4 (bytes) - 4 (bytes of padding) If the callee is as follows: int foo(int a, int b, ...){ ... } ... then the named arguments should be copied to the following location: current_position - 4 (for R2-R5) * 4 (bytes) - 0 (bytes of padding) 4. After any named arguments have been copied, copy all the registers that could have been used to pass unnamed arguments on the stack. If the number of registers is odd, leave 4 bytes of padding and then start copying them on the stack; if the number is even, no padding is required. This constitutes the register-saved area. If padding is required, ensure that the start location of padding is 8-byte aligned. If no padding is required, ensure that the start location of the on-stack copy of the first register which might have a variable argument is 8-byte aligned. 5. Decrement the stack pointer by the size of register saved area plus the padding. For example, if the callee is as follows: int foo(int a, ...){ ... } ; ... then the decrement value should be the following: 5 (for R1-R5) * 4 (bytes) + 4 (bytes of padding) = 24 bytes The decrement should be performed before the allocframe instruction. Increment the stack-pointer back by the same amount before returning from the function.
98 lines
4.8 KiB
LLVM
98 lines
4.8 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv62 -mtriple=hexagon-unknown-linux-musl -O0 < %s | FileCheck %s
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; CHECK-LABEL: foo:
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; Check function prologue generation
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; CHECK: r29 = add(r29,#-24)
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; CHECK: memw(r29+#4) = r1
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; CHECK: memw(r29+#8) = r2
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; CHECK: memw(r29+#12) = r3
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; CHECK: memw(r29+#16) = r4
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; CHECK: memw(r29+#20) = r5
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; CHECK: r29 = add(r29,#24)
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%struct.AAA = type { i32, i32, i32, i32 }
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%struct.__va_list_tag = type { i8*, i8*, i8* }
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@aaa = global %struct.AAA { i32 100, i32 200, i32 300, i32 400 }, align 4
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@.str = private unnamed_addr constant [13 x i8] c"result = %d\0A\00", align 1
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; Function Attrs: nounwind
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define i32 @foo(i32 %xx, ...) #0 {
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entry:
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%ap = alloca [1 x %struct.__va_list_tag], align 8
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%arraydecay1 = bitcast [1 x %struct.__va_list_tag]* %ap to i8*
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call void @llvm.va_start(i8* %arraydecay1)
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%__current_saved_reg_area_pointer_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0, i32 0
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%__current_saved_reg_area_pointer = load i8*, i8** %__current_saved_reg_area_pointer_p, align 8
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%__saved_reg_area_end_pointer_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0, i32 1
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%__saved_reg_area_end_pointer = load i8*, i8** %__saved_reg_area_end_pointer_p, align 4
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%__new_saved_reg_area_pointer = getelementptr i8, i8* %__current_saved_reg_area_pointer, i32 4
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%0 = icmp sgt i8* %__new_saved_reg_area_pointer, %__saved_reg_area_end_pointer
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%__overflow_area_pointer_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0, i32 2
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%__overflow_area_pointer = load i8*, i8** %__overflow_area_pointer_p, align 8
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br i1 %0, label %vaarg.on_stack, label %vaarg.end
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vaarg.on_stack: ; preds = %entry
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%__overflow_area_pointer.next = getelementptr i8, i8* %__overflow_area_pointer, i32 4
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store i8* %__overflow_area_pointer.next, i8** %__overflow_area_pointer_p, align 8
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br label %vaarg.end
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vaarg.end: ; preds = %entry, %vaarg.on_stack
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%__overflow_area_pointer5 = phi i8* [ %__overflow_area_pointer.next, %vaarg.on_stack ], [ %__overflow_area_pointer, %entry ]
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%storemerge32 = phi i8* [ %__overflow_area_pointer.next, %vaarg.on_stack ], [ %__new_saved_reg_area_pointer, %entry ]
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%vaarg.addr.in = phi i8* [ %__overflow_area_pointer, %vaarg.on_stack ], [ %__current_saved_reg_area_pointer, %entry ]
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store i8* %storemerge32, i8** %__current_saved_reg_area_pointer_p, align 8
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%vaarg.addr = bitcast i8* %vaarg.addr.in to i32*
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%1 = load i32, i32* %vaarg.addr, align 4
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%__overflow_area_pointer_p4 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0, i32 2
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%__overflow_area_pointer.next6 = getelementptr i8, i8* %__overflow_area_pointer5, i32 16
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store i8* %__overflow_area_pointer.next6, i8** %__overflow_area_pointer_p4, align 8
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%bbb.sroa.1.0.idx27 = getelementptr inbounds i8, i8* %__overflow_area_pointer5, i32 12
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%2 = bitcast i8* %bbb.sroa.1.0.idx27 to i32*
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%bbb.sroa.1.0.copyload = load i32, i32* %2, align 4
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%add8 = add nsw i32 %bbb.sroa.1.0.copyload, %1
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%__new_saved_reg_area_pointer15 = getelementptr i8, i8* %storemerge32, i32 4
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%3 = icmp sgt i8* %__new_saved_reg_area_pointer15, %__saved_reg_area_end_pointer
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br i1 %3, label %vaarg.on_stack17, label %vaarg.end21
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vaarg.on_stack17: ; preds = %vaarg.end
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%__overflow_area_pointer.next20 = getelementptr i8, i8* %__overflow_area_pointer5, i32 20
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store i8* %__overflow_area_pointer.next20, i8** %__overflow_area_pointer_p4, align 8
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br label %vaarg.end21
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vaarg.end21: ; preds = %vaarg.end, %vaarg.on_stack17
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%storemerge = phi i8* [ %__overflow_area_pointer.next20, %vaarg.on_stack17 ], [ %__new_saved_reg_area_pointer15, %vaarg.end ]
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%vaarg.addr22.in = phi i8* [ %__overflow_area_pointer.next6, %vaarg.on_stack17 ], [ %storemerge32, %vaarg.end ]
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store i8* %storemerge, i8** %__current_saved_reg_area_pointer_p, align 8
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%vaarg.addr22 = bitcast i8* %vaarg.addr22.in to i32*
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%4 = load i32, i32* %vaarg.addr22, align 4
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%add23 = add nsw i32 %add8, %4
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call void @llvm.va_end(i8* %arraydecay1)
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ret i32 %add23
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}
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; Function Attrs: nounwind
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declare void @llvm.va_start(i8*) #1
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; Function Attrs: nounwind
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declare void @llvm.va_end(i8*) #1
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%call = tail call i32 (i32, ...) @foo(i32 undef, i32 2, %struct.AAA* byval align 4 @aaa, i32 4)
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%call1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), i32 %call) #1
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ret i32 %call
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}
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; Function Attrs: nounwind
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declare i32 @printf(i8* nocapture readonly, ...) #0
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attributes #0 = { nounwind }
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!llvm.ident = !{!0}
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!0 = !{!"Clang 3.1"}
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