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fe292b0d36
This patch provides optimization of bit manipulation operations by enabling the +experimental-b target feature. It adds matching of single block patterns of instructions to specific bit-manip instructions from the single-bit subset (zbs subextension) of the experimental B extension of RISC-V. It adds also the correspondent codegen tests. This patch is based on Claire Wolf's proposal for the bit manipulation extension of RISCV: https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf Differential Revision: https://reviews.llvm.org/D79874
236 lines
5.7 KiB
LLVM
236 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IB
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64IBS
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define signext i32 @sbclr_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sbclr_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sllw a1, a2, a1
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; RV64I-NEXT: not a1, a1
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbclr_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbclrw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclr_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbclrw a0, a0, a1
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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%neg = xor i32 %shl, -1
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%and1 = and i32 %neg, %a
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ret i32 %and1
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}
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define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sbclr_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sll a1, a2, a1
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; RV64I-NEXT: not a1, a1
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbclr_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbclr a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbclr_i64:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbclr a0, a0, a1
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; RV64IBS-NEXT: ret
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%and = and i64 %b, 63
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%shl = shl nuw i64 1, %and
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%neg = xor i64 %shl, -1
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%and1 = and i64 %neg, %a
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ret i64 %and1
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}
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define signext i32 @sbset_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sbset_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sllw a1, a2, a1
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbset_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbsetw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbsetw a0, a0, a1
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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%or = or i32 %shl, %a
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ret i32 %or
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}
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define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sbset_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sll a1, a2, a1
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbset_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbset a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbset_i64:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbset a0, a0, a1
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; RV64IBS-NEXT: ret
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%conv = and i64 %b, 63
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%shl = shl nuw i64 1, %conv
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%or = or i64 %shl, %a
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ret i64 %or
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}
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define signext i32 @sbinv_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sbinv_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sllw a1, a2, a1
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; RV64I-NEXT: xor a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbinv_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbinvw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbinv_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbinvw a0, a0, a1
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shl = shl nuw i32 1, %and
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%xor = xor i32 %shl, %a
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ret i32 %xor
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}
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define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sbinv_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a2, zero, 1
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; RV64I-NEXT: sll a1, a2, a1
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; RV64I-NEXT: xor a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbinv_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbinv a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbinv_i64:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbinv a0, a0, a1
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; RV64IBS-NEXT: ret
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%conv = and i64 %b, 63
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%shl = shl nuw i64 1, %conv
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%xor = xor i64 %shl, %a
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ret i64 %xor
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}
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define signext i32 @sbext_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: sbext_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srlw a0, a0, a1
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbext_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbextw a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbext_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbextw a0, a0, a1
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; RV64IBS-NEXT: ret
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%and = and i32 %b, 31
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%shr = lshr i32 %a, %and
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%and1 = and i32 %shr, 1
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ret i32 %and1
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}
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define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: sbext_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbext_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbext a0, a0, a1
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbext_i64:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbext a0, a0, a1
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; RV64IBS-NEXT: ret
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%conv = and i64 %b, 63
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%shr = lshr i64 %a, %conv
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%and1 = and i64 %shr, 1
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ret i64 %and1
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}
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define signext i32 @sbexti_i32(i32 signext %a) nounwind {
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; RV64I-LABEL: sbexti_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 5
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbexti_i32:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbexti a0, a0, 5
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbexti_i32:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbexti a0, a0, 5
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; RV64IBS-NEXT: ret
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%shr = lshr i32 %a, 5
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%and = and i32 %shr, 1
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ret i32 %and
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}
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define i64 @sbexti_i64(i64 %a) nounwind {
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; RV64I-LABEL: sbexti_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srli a0, a0, 5
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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;
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; RV64IB-LABEL: sbexti_i64:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: sbexti a0, a0, 5
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; RV64IB-NEXT: ret
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;
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; RV64IBS-LABEL: sbexti_i64:
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; RV64IBS: # %bb.0:
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; RV64IBS-NEXT: sbexti a0, a0, 5
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; RV64IBS-NEXT: ret
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%shr = lshr i64 %a, 5
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%and = and i64 %shr, 1
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ret i64 %and
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}
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