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53cca02b90
Updated the AArch64 tests the best I could with my vague, inferred understanding of AArch64 register banks. As far as I can tell, there is only one 32-bit/64-bit type which will use the gpr register bank, so we have to use the fpr bank for the other operand.
40 lines
1.2 KiB
YAML
40 lines
1.2 KiB
YAML
#RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: global-isel, amdgpu-registered-target
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---
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name: test_bitcast
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0:
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; CHECK: Bad machine code: bitcast cannot convert between pointers and other types
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%0:_(s64) = G_IMPLICIT_DEF
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%1:_(p0) = G_BITCAST %0
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; CHECK: Bad machine code: bitcast cannot convert between pointers and other
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%2:_(p0) = G_IMPLICIT_DEF
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%3:_(s64) = G_BITCAST %2
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; CHECK: Bad machine code: bitcast sizes must match
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%4:_(s32) = G_IMPLICIT_DEF
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%5:_(s64) = G_BITCAST %4
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; CHECK: Bad machine code: bitcast sizes must match
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%6:_(s32) = G_IMPLICIT_DEF
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%7:_(<3 x s8>) = G_BITCAST %6
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; CHECK: Bad machine code: bitcast sizes must match
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%8:_(p1) = G_IMPLICIT_DEF
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%9:_(p3) = G_BITCAST %8
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; CHECK: Bad machine code: bitcast sizes must match
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%10:_(p1) = G_IMPLICIT_DEF
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%11:_(p3) = G_BITCAST %8
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; CHECK: Bad machine code: bitcast must change the type
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%12:_(s64) = G_BITCAST %0
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...
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