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llvm-mirror/lib/CodeGen/SelectionDAG
Sanjay Patel 1a03ebd2a9 [SDAG] reduce code duplication for extend_vec_inreg combines; NFC
These are identical so far, and I was looking at adding a fold
for a pattern with scalar_to_vector which would also nd up duplicated.
2021-05-14 08:29:57 -04:00
..
CMakeLists.txt
DAGCombiner.cpp [SDAG] reduce code duplication for extend_vec_inreg combines; NFC 2021-05-14 08:29:57 -04:00
FastISel.cpp IR+AArch64: add a "swiftasync" argument attribute. 2021-05-14 11:43:58 +01:00
FunctionLoweringInfo.cpp [NFC] Wisely nest dyn_cast in FunctionLoweringInfo 2021-03-16 10:22:44 +01:00
InstrEmitter.cpp [DebugInfo] Emit DBG_VALUE_LIST from ISel 2021-03-09 12:17:39 +00:00
InstrEmitter.h [DebugInfo] Emit DBG_VALUE_LIST from ISel 2021-03-09 12:17:39 +00:00
LegalizeDAG.cpp [SelectionDAG][AArch64][SVE] Perform SETCC condition legalization in LegalizeVectorOps 2021-03-29 15:32:25 +01:00
LegalizeFloatTypes.cpp Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0" 2021-05-03 21:48:20 +01:00
LegalizeIntegerTypes.cpp [SelectionDAG] Use a VTSDNode to store the saturation width for FP_TO_SINT_SAT/FP_TO_UINT_SAT 2021-04-27 14:38:42 -07:00
LegalizeTypes.cpp [SelectionDAG] Use range-based for loops (NFC) 2021-02-09 22:14:30 -08:00
LegalizeTypes.h Revert "[CodeGen][ARM] Implement atomicrmw as pseudo operations at -O0" 2021-05-03 21:48:20 +01:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
LegalizeVectorTypes.cpp [DAGCombiner] Allow operand of step_vector to be negative. 2021-04-22 20:58:03 +08:00
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp [DebugInfo] Fix crash when emitting an invalidated SDDbgValue 2021-05-07 13:13:56 +01:00
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp [SelectionDAG] Use range-based for loops (NFC) 2021-02-09 22:14:30 -08:00
SDNodeDbgValue.h [DAG] Ensure all SD classes consistently return a const reference with getDebugLoc(). NFCI. 2021-05-07 14:48:23 +01:00
SelectionDAG.cpp Revert "[SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics" 2021-05-12 09:46:18 -05:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp IR+AArch64: add a "swiftasync" argument attribute. 2021-05-14 11:43:58 +01:00
SelectionDAGBuilder.h Support unwinding from inline assembly 2021-05-13 19:13:03 +01:00
SelectionDAGDumper.cpp [IR][SVE] Add new llvm.experimental.stepvector intrinsic 2021-03-23 10:43:35 +00:00
SelectionDAGISel.cpp [TableGen] Use sign rotated VBR for OPC_EmitInteger. 2021-05-02 12:40:44 -07:00
SelectionDAGPrinter.cpp [SelectionDAG] Drop unnecessary const from a return type (NFC) 2021-02-07 09:49:33 -08:00
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp [GC][NFC] Move GCStrategy from CodeGen to IR 2021-05-13 12:31:59 +07:00
StatepointLowering.h More precisely type code used for gc.relocate assertions [nfc] 2021-04-06 11:27:36 -07:00
TargetLowering.cpp IR+AArch64: add a "swiftasync" argument attribute. 2021-05-14 11:43:58 +01:00