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llvm-mirror/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-c.ll
Roman Lebedev 1802097fe9 [InstCombine] dropRedundantMaskingOfLeftShiftInput(): truncation (PR42563) 
Summary:
That fold keeps growing and growing :(
I think this may be one of the last pieces for it.

Since D67677/D67725, the fold knowns the general form
of the pattern - where some masking is needed:
https://rise4fun.com/Alive/F5R
https://rise4fun.com/Alive/gslRa

But there is one more huge piece missing - if you are extracting some bits,
it is not impossible that the origin is wider than the extraction,
i.e. there may be a truncation. And we don't deal with that yet.

But we can, and the generalization remains fully identical:
https://rise4fun.com/Alive/Uar
https://rise4fun.com/Alive/5SW

After a preparatory cleanup i think the diff looks rather clean.

One missing piece is that in some patterns (especially pat. b),
`-1` only needs to be `-1` in final type, but that is for later..

https://bugs.llvm.org/show_bug.cgi?id=42563

Reviewers: spatel, nikic

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69125
2019-11-05 12:41:26 +03:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -instcombine -S | FileCheck %s
; If we have some pattern that leaves only some low bits set, and then performs
; left-shift of those bits, we can combine those two shifts into a shift+mask.
; There are many variants to this pattern:
; c) (trunc ((x & (-1 >> maskNbits)))) << shiftNbits
; simplify to:
; ((trunc(x)) << shiftNbits) & (-1 >> ((-(maskNbits+shiftNbits))+32))
; Simple tests.
declare void @use32(i32)
declare void @use64(i64)
define i32 @t0_basic(i64 %x, i32 %nbits) {
; CHECK-LABEL: @t0_basic(
; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
; CHECK-NEXT: [[T1:%.*]] = lshr i64 -1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
; CHECK-NEXT: call void @use64(i64 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T2]]
; CHECK-NEXT: [[T5:%.*]] = and i32 [[TMP2]], 2147483647
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = zext i32 %nbits to i64
%t1 = lshr i64 -1, %t0
%t2 = add i32 %nbits, -33
call void @use64(i64 %t0)
call void @use64(i64 %t1)
call void @use32(i32 %t2)
%t3 = and i64 %t1, %x
%t4 = trunc i64 %t3 to i32
%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
ret i32 %t5
}
; Vectors
declare void @use8xi32(<8 x i32>)
declare void @use8xi64(<8 x i64>)
define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t1_vec_splat(
; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33>
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = zext <8 x i32> %nbits to <8 x i64>
%t1 = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, %t0
%t2 = add <8 x i32> %nbits, <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33>
call void @use8xi64(<8 x i64> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi32(<8 x i32> %t2)
%t3 = and <8 x i64> %t1, %x
%t4 = trunc <8 x i64> %t3 to <8 x i32>
%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
ret <8 x i32> %t5
}
define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t2_vec_splat_undef(
; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 undef, i32 -33>
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 undef, i32 2147483647>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = zext <8 x i32> %nbits to <8 x i64>
%t1 = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>, %t0
%t2 = add <8 x i32> %nbits, <i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 -33, i32 undef, i32 -33>
call void @use8xi64(<8 x i64> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi32(<8 x i32> %t2)
%t3 = and <8 x i64> %t1, %x
%t4 = trunc <8 x i64> %t3 to <8 x i32>
%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
ret <8 x i32> %t5
}
define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) {
; CHECK-LABEL: @t3_vec_nonsplat(
; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64>
; CHECK-NEXT: [[T1:%.*]] = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[NBITS]], <i32 -64, i32 -63, i32 -33, i32 -32, i32 63, i32 64, i32 undef, i32 65>
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T0]])
; CHECK-NEXT: call void @use8xi64(<8 x i64> [[T1]])
; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T2]])
; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i64> [[X:%.*]] to <8 x i32>
; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i32> [[TMP1]], [[T2]]
; CHECK-NEXT: [[T5:%.*]] = and <8 x i32> [[TMP2]], <i32 undef, i32 1, i32 2147483647, i32 -1, i32 -1, i32 -1, i32 undef, i32 undef>
; CHECK-NEXT: ret <8 x i32> [[T5]]
;
%t0 = zext <8 x i32> %nbits to <8 x i64>
%t1 = lshr <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 undef, i64 -1>, %t0
%t2 = add <8 x i32> %nbits, <i32 -64, i32 -63, i32 -33, i32 -32, i32 63, i32 64, i32 undef, i32 65>
call void @use8xi64(<8 x i64> %t0)
call void @use8xi64(<8 x i64> %t1)
call void @use8xi32(<8 x i32> %t2)
%t3 = and <8 x i64> %t1, %x
%t4 = trunc <8 x i64> %t3 to <8 x i32>
%t5 = shl <8 x i32> %t4, %t2 ; shift is smaller than mask
ret <8 x i32> %t5
}
; Extra uses.
define i32 @n4_extrause0(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n4_extrause0(
; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
; CHECK-NEXT: [[T1:%.*]] = lshr i64 -1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
; CHECK-NEXT: call void @use64(i64 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = and i64 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = zext i32 %nbits to i64
%t1 = lshr i64 -1, %t0
%t2 = add i32 %nbits, -33
call void @use64(i64 %t0)
call void @use64(i64 %t1)
call void @use32(i32 %t2)
%t3 = and i64 %t1, %x
call void @use64(i64 %t3)
%t4 = trunc i64 %t3 to i32
%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
ret i32 %t5
}
define i32 @n5_extrause1(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n5_extrause1(
; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
; CHECK-NEXT: [[T1:%.*]] = lshr i64 -1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
; CHECK-NEXT: call void @use64(i64 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = and i64 [[T1]], [[X:%.*]]
; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = zext i32 %nbits to i64
%t1 = lshr i64 -1, %t0
%t2 = add i32 %nbits, -33
call void @use64(i64 %t0)
call void @use64(i64 %t1)
call void @use32(i32 %t2)
%t3 = and i64 %t1, %x
%t4 = trunc i64 %t3 to i32
call void @use32(i32 %t4)
%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
ret i32 %t5
}
define i32 @n6_extrause2(i64 %x, i32 %nbits) {
; CHECK-LABEL: @n6_extrause2(
; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64
; CHECK-NEXT: [[T1:%.*]] = lshr i64 -1, [[T0]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -33
; CHECK-NEXT: call void @use64(i64 [[T0]])
; CHECK-NEXT: call void @use64(i64 [[T1]])
; CHECK-NEXT: call void @use32(i32 [[T2]])
; CHECK-NEXT: [[T3:%.*]] = and i64 [[T1]], [[X:%.*]]
; CHECK-NEXT: call void @use64(i64 [[T3]])
; CHECK-NEXT: [[T4:%.*]] = trunc i64 [[T3]] to i32
; CHECK-NEXT: call void @use32(i32 [[T4]])
; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[T2]]
; CHECK-NEXT: ret i32 [[T5]]
;
%t0 = zext i32 %nbits to i64
%t1 = lshr i64 -1, %t0
%t2 = add i32 %nbits, -33
call void @use64(i64 %t0)
call void @use64(i64 %t1)
call void @use32(i32 %t2)
%t3 = and i64 %t1, %x
call void @use64(i64 %t3)
%t4 = trunc i64 %t3 to i32
call void @use32(i32 %t4)
%t5 = shl i32 %t4, %t2 ; shift is smaller than mask
ret i32 %t5
}
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