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This is a series of patches to enable adding of machine sched models for ARM processors easier and compact. They define new sched-readwrites for groups of ARM instructions. This has been missing so far, and as a consequence, machine scheduler models for individual sub-targets have tended to be larger than they needed to be. The current patch focuses on floating-point instructions. Reviewers: Diana Picus (rovka), Renato Golin (rengolin) Differential Revision: https://reviews.llvm.org/D28194 llvm-svn: 292825
70 lines
2.1 KiB
LLVM
70 lines
2.1 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
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; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A9
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; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
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; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT
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; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > \
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; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R52
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;
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; Check the latency of instructions for processors with sched-models
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;
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; Function Attrs: norecurse nounwind readnone
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define i32 @foo(float %a, float %b, float %c, i32 %d) local_unnamed_addr #0 {
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entry:
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK_A9: VADDS
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; CHECK_SWIFT: VADDfd
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; CHECK_R52: VADDS
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; CHECK_A9: Latency : 5
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; CHECK_SWIFT: Latency : 4
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; CHECK_R52: Latency : 6
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;
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; CHECK_A9: VMULS
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; CHECK_SWIFT: VMULfd
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; CHECK_R52: VMULS
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; CHECK_SWIFT: Latency : 4
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; CHECK_A9: Latency : 6
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; CHECK_R52: Latency : 6
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;
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; CHECK: VDIVS
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; CHECK_SWIFT: Latency : 17
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; CHECK_A9: Latency : 16
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; CHECK_R52: Latency : 7
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;
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; CHECK: VCVTDS
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; CHECK_SWIFT: Latency : 4
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; CHECK_A9: Latency : 5
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; CHECK_R52: Latency : 6
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;
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; CHECK: VADDD
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; CHECK_SWIFT: Latency : 6
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; CHECK_A9: Latency : 5
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; CHECK_R52: Latency : 6
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;
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; CHECK: VMULD
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; CHECK_SWIFT: Latency : 6
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; CHECK_A9: Latency : 7
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; CHECK_R52: Latency : 6
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;
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; CHECK: VDIVD
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; CHECK_SWIFT: Latency : 32
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; CHECK_A9: Latency : 26
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; CHECK_R52: Latency : 17
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;
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; CHECK: VTOSIZD
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; CHECK_SWIFT: Latency : 4
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; CHECK_A9: Latency : 5
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; CHECK_R52: Latency : 6
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;
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%add = fadd float %a, %b
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%mul = fmul float %add, %add
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%div = fdiv float %mul, %b
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%conv1 = fpext float %div to double
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%add3 = fadd double %conv1, %conv1
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%mul4 = fmul double %add3, %add3
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%div5 = fdiv double %mul4, %conv1
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%conv6 = fptosi double %div5 to i32
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ret i32 %conv6
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}
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