Tony Jiang 7cd663b80c [PowerPC] Expand ISEL instruction into if-then-else sequence. ... Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154		2017-01-16 20:12:26 +00:00
..
AArch64	[AArch64] Falkor supports Rounding Double Multiply Add/Subtract instructions.	2017-01-16 16:28:43 +00:00
AMDGPU	[AMDGPU] Implement f16 fcopysign and fcopysign(f32, f64)	2017-01-13 19:49:25 +00:00
ARM	[SelectionDAG] Add support for BITREVERSE constant folding	2017-01-16 13:39:00 +00:00
AVR	[AVR] Implement TargetLoweing::getRegisterByName	2017-01-07 23:39:47 +00:00
BPF
Generic	Reverted: Track validity of pass results	2017-01-15 10:23:18 +00:00
Hexagon
Inputs
Lanai
Mips	Reverted: Track validity of pass results	2017-01-15 10:23:18 +00:00
MIR	[AArch64] Fold some filled/spilled subreg COPYs	2017-01-05 21:51:42 +00:00
MSP430
NVPTX	[NVPTX] Add fptosi tests to convert-fp.ll.	2017-01-15 16:55:54 +00:00
PowerPC	[PowerPC] Expand ISEL instruction into if-then-else sequence.	2017-01-16 20:12:26 +00:00
SPARC	Check for register clobbers when merging a vreg live range with a	2017-01-13 19:08:36 +00:00
SystemZ	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
Thumb2	ARM: match GCC's behaviour for builtins	2017-01-13 16:25:33 +00:00
WebAssembly	Revert "CodeGen: Allow small copyable blocks to "break" the CFG."	2017-01-11 19:55:19 +00:00
WinEH
X86	[SelectionDAG] Add knownbits support for BITREVERSE	2017-01-16 14:49:26 +00:00
XCore