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271 lines
8.6 KiB
C++
271 lines
8.6 KiB
C++
//===-- LanaiRegisterInfo.cpp - Lanai Register Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Lanai implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "LanaiRegisterInfo.h"
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#include "Lanai.h"
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#include "LanaiSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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#include "LanaiGenRegisterInfo.inc"
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using namespace llvm;
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LanaiRegisterInfo::LanaiRegisterInfo() : LanaiGenRegisterInfo(Lanai::RCA) {}
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const uint16_t *
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LanaiRegisterInfo::getCalleeSavedRegs(const MachineFunction * /*MF*/) const {
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return CSR_SaveList;
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}
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BitVector LanaiRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(Lanai::R0);
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Reserved.set(Lanai::R1);
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Reserved.set(Lanai::PC);
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Reserved.set(Lanai::R2);
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Reserved.set(Lanai::SP);
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Reserved.set(Lanai::R4);
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Reserved.set(Lanai::FP);
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Reserved.set(Lanai::R5);
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Reserved.set(Lanai::RR1);
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Reserved.set(Lanai::R10);
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Reserved.set(Lanai::RR2);
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Reserved.set(Lanai::R11);
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Reserved.set(Lanai::RCA);
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Reserved.set(Lanai::R15);
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if (hasBasePointer(MF))
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Reserved.set(getBaseRegister());
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return Reserved;
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}
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bool LanaiRegisterInfo::requiresRegisterScavenging(
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const MachineFunction & /*MF*/) const {
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return true;
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}
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bool LanaiRegisterInfo::trackLivenessAfterRegAlloc(
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const MachineFunction & /*MF*/) const {
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return true;
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}
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static bool isALUArithLoOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::ADD_I_LO:
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case Lanai::SUB_I_LO:
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case Lanai::ADD_F_I_LO:
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case Lanai::SUB_F_I_LO:
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case Lanai::ADDC_I_LO:
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case Lanai::SUBB_I_LO:
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case Lanai::ADDC_F_I_LO:
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case Lanai::SUBB_F_I_LO:
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return true;
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default:
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return false;
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}
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}
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static unsigned getOppositeALULoOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::ADD_I_LO:
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return Lanai::SUB_I_LO;
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case Lanai::SUB_I_LO:
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return Lanai::ADD_I_LO;
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case Lanai::ADD_F_I_LO:
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return Lanai::SUB_F_I_LO;
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case Lanai::SUB_F_I_LO:
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return Lanai::ADD_F_I_LO;
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case Lanai::ADDC_I_LO:
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return Lanai::SUBB_I_LO;
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case Lanai::SUBB_I_LO:
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return Lanai::ADDC_I_LO;
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case Lanai::ADDC_F_I_LO:
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return Lanai::SUBB_F_I_LO;
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case Lanai::SUBB_F_I_LO:
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return Lanai::ADDC_F_I_LO;
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default:
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llvm_unreachable("Invalid ALU lo opcode");
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}
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}
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static unsigned getRRMOpcodeVariant(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDBs_RI:
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return Lanai::LDBs_RR;
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case Lanai::LDBz_RI:
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return Lanai::LDBz_RR;
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case Lanai::LDHs_RI:
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return Lanai::LDHs_RR;
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case Lanai::LDHz_RI:
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return Lanai::LDHz_RR;
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case Lanai::LDW_RI:
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return Lanai::LDW_RR;
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case Lanai::STB_RI:
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return Lanai::STB_RR;
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case Lanai::STH_RI:
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return Lanai::STH_RR;
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case Lanai::SW_RI:
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return Lanai::SW_RR;
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default:
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llvm_unreachable("Opcode has no RRM variant");
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}
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}
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void LanaiRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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bool HasFP = TFI->hasFP(MF);
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DebugLoc DL = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum + 1).getImm();
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// Addressable stack objects are addressed using neg. offsets from fp
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// or pos. offsets from sp/basepointer
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if (!HasFP || (needsStackRealignment(MF) && FrameIndex >= 0))
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Offset += MF.getFrameInfo().getStackSize();
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unsigned FrameReg = getFrameRegister(MF);
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if (FrameIndex >= 0) {
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if (hasBasePointer(MF))
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FrameReg = getBaseRegister();
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else if (needsStackRealignment(MF))
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FrameReg = Lanai::SP;
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}
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// Replace frame index with a frame pointer reference.
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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// Otherwise scavenge a register and encode it into a MOVHI, OR_I_LO sequence.
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if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) ||
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!isInt<16>(Offset)) {
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assert(RS && "Register scavenging must be on");
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unsigned Reg = RS->FindUnusedReg(&Lanai::GPRRegClass);
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if (!Reg)
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Reg = RS->scavengeRegister(&Lanai::GPRRegClass, II, SPAdj);
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assert(Reg && "Register scavenger failed");
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bool HasNegOffset = false;
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// ALU ops have unsigned immediate values. If the Offset is negative, we
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// negate it here and reverse the opcode later.
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if (Offset < 0) {
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HasNegOffset = true;
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Offset = -Offset;
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}
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if (!isInt<16>(Offset)) {
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// Reg = hi(offset) | lo(offset)
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BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
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.addImm(static_cast<uint32_t>(Offset) >> 16);
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BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
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.addReg(Reg)
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.addImm(Offset & 0xffffU);
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} else {
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// Reg = mov(offset)
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BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
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.addImm(0)
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.addImm(Offset);
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}
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// Reg = FrameReg OP Reg
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if (MI.getOpcode() == Lanai::ADD_I_LO) {
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BuildMI(*MI.getParent(), II, DL,
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HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R),
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MI.getOperand(0).getReg())
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.addReg(FrameReg)
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.addReg(Reg)
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.addImm(LPCC::ICC_T);
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MI.eraseFromParent();
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return;
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}
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if (isSPLSOpcode(MI.getOpcode()) || isRMOpcode(MI.getOpcode())) {
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MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode())));
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if (HasNegOffset) {
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// Change the ALU op (operand 3) from LPAC::ADD (the default) to
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// LPAC::SUB with the already negated offset.
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assert((MI.getOperand(3).getImm() == LPAC::ADD) &&
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"Unexpected ALU op in RRM instruction");
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MI.getOperand(3).setImm(LPAC::SUB);
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}
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} else
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llvm_unreachable("Unexpected opcode in frame index operation");
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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MI.getOperand(FIOperandNum + 1)
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.ChangeToRegister(Reg, /*isDef=*/false, /*isImp=*/false,
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/*isKill=*/true);
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return;
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}
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// ALU arithmetic ops take unsigned immediates. If the offset is negative,
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// we replace the instruction with one that inverts the opcode and negates
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// the immediate.
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if ((Offset < 0) && isALUArithLoOpcode(MI.getOpcode())) {
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unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode());
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// We know this is an ALU op, so we know the operands are as follows:
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// 0: destination register
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// 1: source register (frame register)
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// 2: immediate
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BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
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MI.getOperand(0).getReg())
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.addReg(FrameReg)
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.addImm(-Offset);
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MI.eraseFromParent();
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} else {
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MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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}
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bool LanaiRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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// When we need stack realignment and there are dynamic allocas, we can't
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// reference off of the stack pointer, so we reserve a base pointer.
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if (needsStackRealignment(MF) && MFI.hasVarSizedObjects())
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return true;
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return false;
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}
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unsigned LanaiRegisterInfo::getRARegister() const { return Lanai::RCA; }
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unsigned
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LanaiRegisterInfo::getFrameRegister(const MachineFunction & /*MF*/) const {
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return Lanai::FP;
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}
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unsigned LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }
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const uint32_t *
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LanaiRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/,
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CallingConv::ID /*CC*/) const {
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return CSR_RegMask;
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}
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