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f46165f928
Summary: Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`. Patch by Andrew Wei Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders Reviewed By: dsanders Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65219 llvm-svn: 369467
35 lines
1.0 KiB
Plaintext
35 lines
1.0 KiB
Plaintext
;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===;
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;
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; Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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; See https://llvm.org/LICENSE.txt for license information.
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; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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;
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;===------------------------------------------------------------------------===;
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;
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; This is an LLVMBuild description file for the components in this subdirectory.
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;
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; For more information on the LLVMBuild system, please see:
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;
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; http://llvm.org/docs/LLVMBuild.html
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;
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;===------------------------------------------------------------------------===;
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[common]
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subdirectories = AsmParser Disassembler TargetInfo MCTargetDesc Utils
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[component_0]
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type = TargetGroup
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name = RISCV
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parent = Target
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has_asmparser = 1
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has_asmprinter = 1
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has_disassembler = 1
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[component_1]
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type = Library
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name = RISCVCodeGen
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parent = RISCV
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required_libraries = Analysis AsmPrinter Core CodeGen MC RISCVDesc
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RISCVInfo RISCVUtils SelectionDAG Support Target GlobalISel
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add_to_library_groups = RISCV
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