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1924b30c0e
- TargetMachine implementation for M68k - ISel, ISched for M68k - Other lowering (e.g. FrameLowering) - AsmPrinter Authors: myhsu, m4yers, glaubitz Differential Revision: https://reviews.llvm.org/D88391
110 lines
3.8 KiB
C++
110 lines
3.8 KiB
C++
//===-- M68kRegisterInfo.h - M68k Register Information Impl --*- C++ --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains the M68k implementation of the TargetRegisterInfo
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/// class.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_M68K_M68KREGISTERINFO_H
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#define LLVM_LIB_TARGET_M68K_M68KREGISTERINFO_H
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#include "M68k.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "M68kGenRegisterInfo.inc"
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namespace llvm {
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class M68kSubtarget;
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class TargetInstrInfo;
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class Type;
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class M68kRegisterInfo : public M68kGenRegisterInfo {
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virtual void anchor();
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/// Physical register used as stack ptr.
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unsigned StackPtr;
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/// Physical register used as frame ptr.
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unsigned FramePtr;
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/// Physical register used as a base ptr in complex stack frames. I.e., when
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/// we need a 3rd base, not just SP and FP, due to variable size stack
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/// objects.
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unsigned BasePtr;
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/// Physical register used to store GOT address if needed.
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unsigned GlobalBasePtr;
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protected:
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const M68kSubtarget &Subtarget;
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public:
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M68kRegisterInfo(const M68kSubtarget &Subtarget);
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
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/// Returns a register class with registers that can be used in forming tail
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/// calls.
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const TargetRegisterClass *
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getRegsForTailCall(const MachineFunction &MF) const;
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/// Return a mega-register of the specified register Reg so its sub-register
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/// of index SubIdx is Reg, its super(or mega) Reg. In other words it will
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/// return a register that is not direct super register but still shares
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/// physical register with Reg.
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/// NOTE not sure about the term though.
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unsigned getMatchingMegaReg(unsigned Reg,
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const TargetRegisterClass *RC) const;
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/// Returns the Register Class of a physical register of the given type,
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/// picking the biggest register class of the right type that contains this
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/// physreg.
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const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
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/// Return index of a register within a register class, otherwise return -1
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int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
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/// Return spill order index of a register, if there is none then trap
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int getSpillRegisterOrder(unsigned Reg) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &MF) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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/// FrameIndex represent objects inside a abstract stack. We must replace
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/// FrameIndex with an stack/frame pointer direct reference.
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void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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/// True if the stack can be realigned for the target.
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bool canRealignStack(const MachineFunction &MF) const override;
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Register getFrameRegister(const MachineFunction &MF) const override;
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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unsigned getGlobalBaseRegister() const { return GlobalBasePtr; }
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const TargetRegisterClass *intRegClass(unsigned Size) const;
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};
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} // end namespace llvm
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#endif
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