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7d6b0c31fc
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
77 lines
2.8 KiB
C++
77 lines
2.8 KiB
C++
//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsSEISELLOWERING_H
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#define MipsSEISELLOWERING_H
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#include "MipsISelLowering.h"
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#include "MipsRegisterInfo.h"
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namespace llvm {
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class MipsSETargetLowering : public MipsTargetLowering {
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public:
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explicit MipsSETargetLowering(MipsTargetMachine &TM);
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void addMSAType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
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virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
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EVT VT) const {
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return false;
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}
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virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
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if (VT == MVT::Untyped)
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return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass :
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&Mips::ACC64RegClass;
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return TargetLowering::getRepRegClassFor(VT);
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}
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private:
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virtual bool
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isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const;
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virtual void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
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SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
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SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned BranchOp) const;
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};
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}
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#endif // MipsSEISELLOWERING_H
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