Sanjay Patel e3955cf340 [TargetLowering] remove fdiv and frem from canOpTrap() (PR29114) ... Assuming the default FP env, we should not treat fdiv and frem any differently in terms of trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env. This matches how we treat these ops in IR with isSafeToSpeculativelyExecute(). There's a similar bug in Constant::canTrap(). This bug manifests in PR29114: https://llvm.org/bugs/show_bug.cgi?id=29114 ...as a sequence of scalar divisions instead of a vector division on x86 for a <3 x float> type. Differential Revision: https://reviews.llvm.org/D23974 llvm-svn: 279970		2016-08-29 13:32:41 +00:00
..
CostTable.h	[modules] Add missing include.	2016-08-19 08:30:42 +00:00
GenericOpcodes.td	GlobalISel: make truncate/extend casts uniform	2016-08-23 21:01:33 +00:00
Target.td	TableGen: Allow custom register operand decoder method	2016-07-18 23:20:46 +00:00
TargetCallingConv.h
TargetCallingConv.td
TargetFrameLowering.h	[IPRA] Set callee saved registers to none for local function when IPRA is enabled.	2016-07-13 23:39:34 +00:00
TargetInstrInfo.h	Recommit 'Remove the restriction that MachineSinking is now stopped by	2016-08-12 03:33:22 +00:00
TargetIntrinsicInfo.h	GlobalISel: support translation of intrinsic calls.	2016-07-29 22:32:36 +00:00
TargetItinerary.td
TargetLowering.h	[TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)	2016-08-29 13:32:41 +00:00
TargetLoweringObjectFile.h	Move code only used by codegen out of MC. NFC.	2016-08-29 12:33:42 +00:00
TargetMachine.h	CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses	2016-08-24 01:52:46 +00:00
TargetOpcodes.def	GlobalISel: make truncate/extend casts uniform	2016-08-23 21:01:33 +00:00
TargetOpcodes.h	[GlobalISel] Don't RegBankSelect target-specific instructions.	2016-08-02 11:41:16 +00:00
TargetOptions.h	Remove MCAsmInfo.h include from TargetOptions.h	2016-07-27 16:03:57 +00:00
TargetRecip.h
TargetRegisterInfo.h	Fixing bug committed in rev. 278321	2016-08-17 11:40:21 +00:00
TargetSchedule.td	Revert "Revert "[misched] Extend scheduler to handle unsupported features""	2016-06-24 08:43:27 +00:00
TargetSelectionDAG.td	[SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround	2016-08-18 20:08:15 +00:00
TargetSubtargetInfo.h	MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not print/parser it	2016-08-24 22:17:45 +00:00