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76 lines
2.4 KiB
C++
76 lines
2.4 KiB
C++
//===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains CellSPU frame information that doesn't fit anywhere else
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// cleanly...
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//
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//===----------------------------------------------------------------------===//
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#if !defined(SPUFRAMEINFO_H)
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "SPURegisterInfo.h"
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namespace llvm {
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class SPUFrameInfo: public TargetFrameInfo {
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const TargetMachine &TM;
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std::pair<unsigned, int> LR[1];
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public:
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SPUFrameInfo(const TargetMachine &tm);
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//! Return a function's saved spill slots
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/*!
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For CellSPU, a function's saved spill slots is just the link register.
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*/
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const std::pair<unsigned, int> *
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getCalleeSaveSpillSlots(unsigned &NumEntries) const;
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//! Stack slot size (16 bytes)
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static int stackSlotSize() {
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return 16;
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}
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//! Maximum frame offset representable by a signed 10-bit integer
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/*!
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This is the maximum frame offset that can be expressed as a 10-bit
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integer, used in D-form addresses.
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*/
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static int maxFrameOffset() {
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return ((1 << 9) - 1) * stackSlotSize();
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}
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//! Minimum frame offset representable by a signed 10-bit integer
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static int minFrameOffset() {
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return -(1 << 9) * stackSlotSize();
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}
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//! Minimum frame size (enough to spill LR + SP)
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static int minStackSize() {
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return (2 * stackSlotSize());
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}
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//! Frame size required to spill all registers plus frame info
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static int fullSpillSize() {
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return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
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}
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//! Number of instructions required to overcome hint-for-branch latency
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/*!
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HBR (hint-for-branch) instructions can be inserted when, for example,
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we know that a given function is going to be called, such as printf(),
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in the control flow graph. HBRs are only inserted if a sufficient number
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of instructions occurs between the HBR and the target. Currently, HBRs
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take 6 cycles, ergo, the magic number 6.
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*/
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static int branchHintPenalty() {
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return 6;
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}
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};
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}
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#define SPUFRAMEINFO_H 1
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#endif
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