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4d25e8bf01
This adds a some more tests, and adds some notes to tests which are using a suboptimal lowering. The constants with suboptimal lowerings seem to be relatively rare in practice, but it might be a fun project to work on improvements. llvm-svn: 331304
375 lines
10 KiB
LLVM
375 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-eabi | FileCheck %s
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;==--------------------------------------------------------------------------==
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; Tests for MOV-immediate implemented with ORR-immediate.
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;==--------------------------------------------------------------------------==
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; 64-bit immed with 32-bit pattern size, rotated by 0.
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define i64 @test64_32_rot0() nounwind {
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; CHECK-LABEL: test64_32_rot0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #30064771079
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; CHECK-NEXT: ret
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ret i64 30064771079
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}
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; 64-bit immed with 32-bit pattern size, rotated by 2.
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define i64 @test64_32_rot2() nounwind {
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; CHECK-LABEL: test64_32_rot2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-4611686002321260541
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; CHECK-NEXT: ret
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ret i64 13835058071388291075
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}
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; 64-bit immed with 4-bit pattern size, rotated by 3.
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define i64 @test64_4_rot3() nounwind {
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; CHECK-LABEL: test64_4_rot3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-1229782938247303442
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; CHECK-NEXT: ret
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ret i64 17216961135462248174
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}
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; 64-bit immed with 64-bit pattern size, many bits.
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define i64 @test64_64_manybits() nounwind {
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; CHECK-LABEL: test64_64_manybits:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #4503599627304960
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; CHECK-NEXT: ret
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ret i64 4503599627304960
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}
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; 64-bit immed with 64-bit pattern size, one bit.
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; FIXME: Prefer movz, so it prints as "mov".
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define i64 @test64_64_onebit() nounwind {
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; CHECK-LABEL: test64_64_onebit:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr x0, xzr, #0x4000000000
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; CHECK-NEXT: ret
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ret i64 274877906944
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}
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; 32-bit immed with 32-bit pattern size, rotated by 16.
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; FIXME: Prefer "movz" instead (so we print as "mov").
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define i32 @test32_32_rot16() nounwind {
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; CHECK-LABEL: test32_32_rot16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, wzr, #0xff0000
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; CHECK-NEXT: ret
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ret i32 16711680
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}
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; 32-bit immed with 2-bit pattern size, rotated by 1.
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define i32 @test32_2_rot1() nounwind {
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; CHECK-LABEL: test32_2_rot1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #-1431655766
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; CHECK-NEXT: ret
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ret i32 2863311530
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}
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;==--------------------------------------------------------------------------==
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; Tests for MOVZ with MOVK.
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;==--------------------------------------------------------------------------==
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define i32 @movz() nounwind {
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; CHECK-LABEL: movz:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w0, #5
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; CHECK-NEXT: ret
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ret i32 5
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}
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define i64 @movz_3movk() nounwind {
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; CHECK-LABEL: movz_3movk:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #22136
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; CHECK-NEXT: movk x0, #43981, lsl #16
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; CHECK-NEXT: movk x0, #4660, lsl #32
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; CHECK-NEXT: movk x0, #5, lsl #48
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; CHECK-NEXT: ret
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ret i64 1427392313513592
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}
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define i64 @movz_movk_skip1() nounwind {
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; CHECK-LABEL: movz_movk_skip1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #1126236160
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; CHECK-NEXT: movk x0, #5, lsl #32
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; CHECK-NEXT: ret
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ret i64 22601072640
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}
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define i64 @movz_skip1_movk() nounwind {
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; CHECK-LABEL: movz_skip1_movk:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #4660
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; CHECK-NEXT: movk x0, #34388, lsl #32
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; CHECK-NEXT: ret
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ret i64 147695335379508
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}
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; FIXME: Prefer "mov w0, #2863311530; lsl x0, x0, #4"
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; or "mov x0, #-6148914691236517206; and x0, x0, #45812984480"
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define i64 @orr_lsl_pattern() nounwind {
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; CHECK-LABEL: orr_lsl_pattern:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #43680
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; CHECK-NEXT: movk x0, #43690, lsl #16
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; CHECK-NEXT: movk x0, #10, lsl #32
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; CHECK-NEXT: ret
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ret i64 45812984480
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}
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; FIXME: prefer "mov x0, #-16639; lsl x0, x0, #24"
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define i64 @mvn_lsl_pattern() nounwind {
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; CHECK-LABEL: mvn_lsl_pattern:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #16777216
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; CHECK-NEXT: movk x0, #65471, lsl #32
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: ret
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ret i64 -279156097024
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}
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; FIXME: prefer "mov w0, #-63; movk x0, #31, lsl #32"
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; or "mov x0, #137438887936; movk x0, #65473"
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define i64 @mvn32_pattern() nounwind {
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; CHECK-LABEL: mvn32_pattern:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #65473
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; CHECK-NEXT: movk x0, #65535, lsl #16
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; CHECK-NEXT: movk x0, #31, lsl #32
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; CHECK-NEXT: ret
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ret i64 137438953409
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}
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; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32"
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define i64 @mvn32_pattern_2() nounwind {
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; CHECK-LABEL: mvn32_pattern_2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #65473
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; CHECK-NEXT: movk x0, #65535, lsl #16
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; CHECK-NEXT: movk x0, #17, lsl #32
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; CHECK-NEXT: ret
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ret i64 77309411265
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}
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;==--------------------------------------------------------------------------==
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; Tests for MOVN with MOVK.
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;==--------------------------------------------------------------------------==
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define i64 @movn() nounwind {
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; CHECK-LABEL: movn:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-42
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; CHECK-NEXT: ret
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ret i64 -42
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}
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define i64 @movn_skip1_movk() nounwind {
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; CHECK-LABEL: movn_skip1_movk:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-60876
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; CHECK-NEXT: movk x0, #65494, lsl #32
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; CHECK-NEXT: ret
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ret i64 -176093720012
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}
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;==--------------------------------------------------------------------------==
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; Tests for ORR with MOVK.
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;==--------------------------------------------------------------------------==
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; rdar://14987673
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define i64 @orr_movk1() nounwind {
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; CHECK-LABEL: orr_movk1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72056494543077120
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: ret
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ret i64 72056498262245120
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}
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define i64 @orr_movk2() nounwind {
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; CHECK-LABEL: orr_movk2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72056494543077120
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; CHECK-NEXT: movk x0, #57005, lsl #48
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; CHECK-NEXT: ret
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ret i64 -2400982650836746496
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}
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define i64 @orr_movk3() nounwind {
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; CHECK-LABEL: orr_movk3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72056494543077120
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; CHECK-NEXT: movk x0, #57005, lsl #32
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; CHECK-NEXT: ret
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ret i64 72020953688702720
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}
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define i64 @orr_movk4() nounwind {
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; CHECK-LABEL: orr_movk4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72056494543077120
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; CHECK-NEXT: movk x0, #57005
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; CHECK-NEXT: ret
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ret i64 72056494543068845
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}
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; rdar://14987618
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define i64 @orr_movk5() nounwind {
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; CHECK-LABEL: orr_movk5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: ret
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ret i64 -71777214836900096
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}
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define i64 @orr_movk6() nounwind {
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; CHECK-LABEL: orr_movk6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: movk x0, #57005, lsl #48
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; CHECK-NEXT: ret
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ret i64 -2400982647117578496
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}
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define i64 @orr_movk7() nounwind {
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; CHECK-LABEL: orr_movk7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #57005, lsl #48
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; CHECK-NEXT: ret
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ret i64 -2400982646575268096
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}
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define i64 @orr_movk8() nounwind {
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; CHECK-LABEL: orr_movk8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #57005
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; CHECK-NEXT: movk x0, #57005, lsl #48
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; CHECK-NEXT: ret
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ret i64 -2400982646575276371
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}
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; rdar://14987715
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define i64 @orr_movk9() nounwind {
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; CHECK-LABEL: orr_movk9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #1152921435887370240
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; CHECK-NEXT: movk x0, #65280
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: ret
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ret i64 1152921439623315200
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}
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define i64 @orr_movk10() nounwind {
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; CHECK-LABEL: orr_movk10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #1152921504606846720
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: ret
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ret i64 1152921504047824640
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}
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define i64 @orr_movk11() nounwind {
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; CHECK-LABEL: orr_movk11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-4503599627370241
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; CHECK-NEXT: movk x0, #57005, lsl #16
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; CHECK-NEXT: movk x0, #65535, lsl #32
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; CHECK-NEXT: ret
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ret i64 -4222125209747201
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}
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define i64 @orr_movk12() nounwind {
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; CHECK-LABEL: orr_movk12:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-4503599627370241
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; CHECK-NEXT: movk x0, #57005, lsl #32
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; CHECK-NEXT: ret
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ret i64 -4258765016661761
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}
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define i64 @orr_movk13() nounwind {
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; CHECK-LABEL: orr_movk13:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #17592169267200
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; CHECK-NEXT: movk x0, #57005
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; CHECK-NEXT: movk x0, #57005, lsl #48
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; CHECK-NEXT: ret
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ret i64 -2401245434149282131
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}
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; rdar://13944082
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define i64 @g() nounwind {
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; CHECK-LABEL: g:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x0, #2
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: ret
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entry:
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ret i64 -281474976710654
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}
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; FIXME: prefer "mov x0, #-549755813888; movk x0, 2048, lsl #16"
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define i64 @orr_movk14() nounwind {
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; CHECK-LABEL: orr_movk14:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #134217728
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; CHECK-NEXT: movk x0, #65408, lsl #32
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: ret
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ret i64 -549621596160
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}
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; FIXME: prefer "mov x0, #549755813887; movk x0, #63487, lsl #16"
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define i64 @orr_movk15() nounwind {
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; CHECK-LABEL: orr_movk15:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #65535
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; CHECK-NEXT: movk x0, #63487, lsl #16
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; CHECK-NEXT: movk x0, #127, lsl #32
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; CHECK-NEXT: ret
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ret i64 549621596159
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}
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; FIXME: prefer "mov x0, #2147483646; orr x0, x0, #36028659580010496"
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define i64 @orr_movk16() nounwind {
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; CHECK-LABEL: orr_movk16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #36028659580010496
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; CHECK-NEXT: movk x0, #65534
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; CHECK-NEXT: movk x0, #32767, lsl #16
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; CHECK-NEXT: ret
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ret i64 36028661727494142
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}
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; FIXME: prefer "mov x0, #-1099511627776; movk x0, #65280, lsl #16"
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define i64 @orr_movk17() nounwind {
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; CHECK-LABEL: orr_movk17:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #-71777214294589696
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; CHECK-NEXT: movk x0, #0
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; CHECK-NEXT: movk x0, #65535, lsl #48
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; CHECK-NEXT: ret
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ret i64 -1095233437696
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}
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; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
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define i64 @orr_movk18() nounwind {
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; CHECK-LABEL: orr_movk18:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, #72340172838076673
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; CHECK-NEXT: movk x0, #256
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; CHECK-NEXT: movk x0, #0, lsl #48
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; CHECK-NEXT: ret
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ret i64 1103823438080
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}
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