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7a5e15697d
The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
48 lines
1.6 KiB
LLVM
48 lines
1.6 KiB
LLVM
; RUN: opt -instcombine -S < %s | FileCheck %s
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declare float @llvm.amdgcn.rcp.f32(float) nounwind readnone
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declare double @llvm.amdgcn.rcp.f64(double) nounwind readnone
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; CHECK-LABEL: @test_constant_fold_rcp_f32_1
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; CHECK-NEXT: ret float 1.000000e+00
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define float @test_constant_fold_rcp_f32_1() nounwind {
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%val = call float @llvm.amdgcn.rcp.f32(float 1.0) nounwind readnone
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ret float %val
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}
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; CHECK-LABEL: @test_constant_fold_rcp_f64_1
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; CHECK-NEXT: ret double 1.000000e+00
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define double @test_constant_fold_rcp_f64_1() nounwind {
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%val = call double @llvm.amdgcn.rcp.f64(double 1.0) nounwind readnone
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ret double %val
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}
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; CHECK-LABEL: @test_constant_fold_rcp_f32_half
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; CHECK-NEXT: ret float 2.000000e+00
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define float @test_constant_fold_rcp_f32_half() nounwind {
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%val = call float @llvm.amdgcn.rcp.f32(float 0.5) nounwind readnone
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ret float %val
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}
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; CHECK-LABEL: @test_constant_fold_rcp_f64_half
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; CHECK-NEXT: ret double 2.000000e+00
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define double @test_constant_fold_rcp_f64_half() nounwind {
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%val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone
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ret double %val
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}
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; CHECK-LABEL: @test_constant_fold_rcp_f32_43
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; CHECK-NEXT: call float @llvm.amdgcn.rcp.f32(float 4.300000e+01)
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define float @test_constant_fold_rcp_f32_43() nounwind {
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%val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
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ret float %val
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}
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; CHECK-LABEL: @test_constant_fold_rcp_f64_43
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; CHECK-NEXT: call double @llvm.amdgcn.rcp.f64(double 4.300000e+01)
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define double @test_constant_fold_rcp_f64_43() nounwind {
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%val = call double @llvm.amdgcn.rcp.f64(double 4.300000e+01) nounwind readnone
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ret double %val
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}
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