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d82a7e0d5a
Pass the Scalability test to VectorType::get in order to be able to deserialize bitcode that contains scalable vector operations Differential Revision: https://reviews.llvm.org/D73144
50 lines
1.9 KiB
LLVM
50 lines
1.9 KiB
LLVM
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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@important_val = extern_weak dso_local global i32, align 4
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; CHECK-LABEL: define <vscale x 4 x i32> @const_shufflevector(
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; CHECK: <vscale x 4 x i32> shufflevector (<vscale x 4 x i32>
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define <vscale x 4 x i32> @const_shufflevector() {
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ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> zeroinitializer,
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<vscale x 4 x i32> undef,
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<vscale x 4 x i32> zeroinitializer)
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}
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; CHECK-LABEL: define <vscale x 4 x i32> @const_shufflevector_ex()
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; CHECK: <vscale x 4 x i32> shufflevector (<vscale x 2 x i32>
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define <vscale x 4 x i32> @const_shufflevector_ex() {
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ret <vscale x 4 x i32> shufflevector (<vscale x 2 x i32> zeroinitializer,
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<vscale x 2 x i32> undef,
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<vscale x 4 x i32> zeroinitializer)
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}
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; CHECK-LABEL: define <vscale x 4 x i32> @non_const_shufflevector(
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; CHECK: %res = shufflevector <vscale x 4 x i32>
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define <vscale x 4 x i32> @non_const_shufflevector(<vscale x 4 x i32> %lhs,
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<vscale x 4 x i32> %rhs) {
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%res = shufflevector <vscale x 4 x i32> %lhs,
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<vscale x 4 x i32> %rhs,
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<vscale x 4 x i32> zeroinitializer
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ret <vscale x 4 x i32> %res
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}
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; CHECK-LABEL: define <vscale x 4 x i32> @const_select()
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; CHECK: <vscale x 4 x i32> select (<vscale x 4 x i1>
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define <vscale x 4 x i32> @const_select() {
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ret <vscale x 4 x i32> select
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(<vscale x 4 x i1> insertelement
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(<vscale x 4 x i1> undef,
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i1 icmp ne (i32* @important_val, i32* null),
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i32 0),
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<vscale x 4 x i32> zeroinitializer,
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<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i32 0))
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}
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