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a9e271942e
Fixes PR41696 The loop-reroll pass generates an invalid IR (or its assertion fails in debug build) if values of the base instruction and other root instructions (terms used in the loop-reroll pass) are used outside the loop block. See IRs written in PR41696 as examples. The current implementation of the loop-reroll pass can reroll only loops that don't have values that are used outside the loop, except reduced values (the last values of reduction chains). This is described in the comment of the `LoopReroll::reroll` function. https://github.com/llvm/llvm-project/blob/llvmorg-10.0.0/llvm/lib/Transforms/Scalar/LoopRerollPass.cpp#L1600 This is checked in the `LoopReroll::DAGRootTracker::validate` function. https://github.com/llvm/llvm-project/blob/llvmorg-10.0.0/llvm/lib/Transforms/Scalar/LoopRerollPass.cpp#L1393 However, the base instruction and other root instructions skip this check in the validation loop. https://github.com/llvm/llvm-project/blob/llvmorg-10.0.0/llvm/lib/Transforms/Scalar/LoopRerollPass.cpp#L1229 Moving the check in front of the skip is the logically simplest fix. However, inserting the check in an earlier stage is better in terms of compilation time of unrerollable loops. This fix inserts the check for the base instruction into the function to validate possible base/root instructions. Check for other root instructions is unnecessary because they don't match any base instructions if they have uses outside the loop. Differential Revision: https://reviews.llvm.org/D79549
61 lines
1.8 KiB
LLVM
61 lines
1.8 KiB
LLVM
; RUN: opt < %s -loop-reroll -S | FileCheck %s
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; Check whether rerolling is rejected if values of the base and root
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; instruction are used outside the loop block.
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; Only the base/root instructions except a loop increment instruction
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define void @test1() {
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entry:
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br label %loop1
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loop1:
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;CHECK-LABEL: loop1:
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;CHECK-NEXT: %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop1 ]
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;CHECK-NEXT: %indvar.1 = add nsw i64 %indvar, 1
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%indvar = phi i64 [ 0, %entry ], [ %indvar.next, %loop1 ]
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%indvar.1 = add nsw i64 %indvar, 1
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%indvar.next = add nsw i64 %indvar, 2
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%cmp = icmp slt i64 %indvar.next, 200
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br i1 %cmp, label %loop1, label %exit
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exit:
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%var1 = phi i64 [ %indvar.1, %loop1 ]
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%var2 = phi i64 [ %indvar, %loop1 ]
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ret void
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}
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; Both the base/root instructions and reduction instructions
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define void @test2() {
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entry:
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br label %loop2
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loop2:
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;CHECK-LABEL: loop2:
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;CHECK-NEXT: %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %loop2 ]
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;CHECK-NEXT: %redvar = phi i32 [ 0, %entry ], [ %add.2, %loop2 ]
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;CHECK-NEXT: %indvar.1 = add nuw nsw i32 %indvar, 1
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;CHECK-NEXT: %indvar.2 = add nuw nsw i32 %indvar, 2
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%indvar = phi i32 [ 0, %entry ], [ %indvar.next, %loop2 ]
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%redvar = phi i32 [ 0, %entry ], [ %add.2, %loop2 ]
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%indvar.1 = add nuw nsw i32 %indvar, 1
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%indvar.2 = add nuw nsw i32 %indvar, 2
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%mul.0 = mul nsw i32 %indvar, %indvar
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%mul.1 = mul nsw i32 %indvar.1, %indvar.1
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%mul.2 = mul nsw i32 %indvar.2, %indvar.2
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%add.0 = add nsw i32 %redvar, %mul.0
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%add.1 = add nsw i32 %add.0, %mul.1
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%add.2 = add nsw i32 %add.1, %mul.2
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%indvar.next = add nuw nsw i32 %indvar, 3
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%cmp = icmp slt i32 %indvar.next, 300
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br i1 %cmp, label %loop2, label %exit
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exit:
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%a = phi i32 [ %indvar, %loop2 ]
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%b = phi i32 [ %indvar.1, %loop2 ]
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%c = phi i32 [ %indvar.2, %loop2 ]
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%x = phi i32 [ %add.2, %loop2 ]
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ret void
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}
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