mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
ae65e281f3
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
66 lines
2.4 KiB
C++
66 lines
2.4 KiB
C++
//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
|
|
// are used to describe target instructions and their operands.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/MC/MCInstrDesc.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
#include "llvm/MC/MCRegisterInfo.h"
|
|
#include "llvm/MC/MCSubtargetInfo.h"
|
|
|
|
using namespace llvm;
|
|
|
|
bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
|
|
std::string &Info) const {
|
|
if (ComplexDeprecationInfo)
|
|
return ComplexDeprecationInfo(MI, STI, Info);
|
|
if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) {
|
|
// FIXME: it would be nice to include the subtarget feature here.
|
|
Info = "deprecated";
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
|
|
const MCRegisterInfo &RI) const {
|
|
if (isBranch() || isCall() || isReturn() || isIndirectBranch())
|
|
return true;
|
|
unsigned PC = RI.getProgramCounter();
|
|
if (PC == 0)
|
|
return false;
|
|
if (hasDefOfPhysReg(MI, PC, RI))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
|
|
const MCRegisterInfo *MRI) const {
|
|
if (const MCPhysReg *ImpDefs = ImplicitDefs)
|
|
for (; *ImpDefs; ++ImpDefs)
|
|
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
|
|
const MCRegisterInfo &RI) const {
|
|
for (int i = 0, e = NumDefs; i != e; ++i)
|
|
if (MI.getOperand(i).isReg() &&
|
|
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
|
|
return true;
|
|
if (variadicOpsAreDefs())
|
|
for (int i = NumOperands - 1, e = MI.getNumOperands(); i != e; ++i)
|
|
if (MI.getOperand(i).isReg() &&
|
|
RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
|
|
return true;
|
|
return hasImplicitDefOfPhysReg(Reg, &RI);
|
|
}
|