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The instruction addi is usually used to post increase the loop indvar, which looks like this: label_X: load x, base(i) ... y = op x ... i = addi i, 1 goto label_X However, for PowerPC, if there are too many vsx instructions that between y = op x and i = addi i, 1, it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve. Reviewed By: jji Differential Revision: https://reviews.llvm.org/D80269
53 lines
1.8 KiB
C++
53 lines
1.8 KiB
C++
//===- PPCMachineScheduler.h - Custom PowerPC MI scheduler --*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom PowerPC MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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/// A MachineSchedStrategy implementation for PowerPC pre RA scheduling.
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class PPCPreRASchedStrategy : public GenericScheduler {
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public:
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PPCPreRASchedStrategy(const MachineSchedContext *C) :
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GenericScheduler(C) {}
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protected:
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void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
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SchedBoundary *Zone) const override;
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private:
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bool biasAddiLoadCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary &Zone) const;
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};
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/// A MachineSchedStrategy implementation for PowerPC post RA scheduling.
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class PPCPostRASchedStrategy : public PostGenericScheduler {
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public:
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PPCPostRASchedStrategy(const MachineSchedContext *C) :
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PostGenericScheduler(C) {}
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protected:
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void initialize(ScheduleDAGMI *Dag) override;
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SUnit *pickNode(bool &IsTopNode) override;
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void enterMBB(MachineBasicBlock *MBB) override;
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void leaveMBB() override;
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void tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) override;
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bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H
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