Tom Stellard 7ea6de8aca MIRParser: Add support for parsing vreg reg alloc hints ... Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26573 llvm-svn: 286911		2016-11-15 00:03:14 +00:00
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AArch64	[AArch64] Compute the Newton series for reciprocals natively	2016-11-14 23:29:01 +00:00
AMDGPU	AMDGPU/SI: Support data types other than V4f32 in image intrinsics	2016-11-14 18:33:18 +00:00
ARM	Recommit: ARM: sort register lists by encoding in push/pop instructions.	2016-11-14 20:28:24 +00:00
AVR
BPF
Generic
Hexagon	[Hexagon] Remove unsafe load instructions that affect Stack Slot Coloring	2016-11-14 17:11:00 +00:00
Inputs
Lanai
Mips
MIR	MIRParser: Add support for parsing vreg reg alloc hints	2016-11-15 00:03:14 +00:00
MSP430
NVPTX
PowerPC	[PPC] Add intrinsic mapping to the xscvhpsp instruction	2016-11-14 18:43:59 +00:00
SPARC	ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()	2016-11-11 01:34:21 +00:00
SystemZ	[SystemZ] Support CL(G)T instructions	2016-11-11 12:48:26 +00:00
Thumb
Thumb2
WebAssembly
WinEH
X86	[X86] Tests exhibiting bad parial reloading behavior. NFC.	2016-11-14 19:58:11 +00:00
XCore