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80d5f68422
Return is now considered a predicable instruction, and is converted to a newly-added CondReturn (which maps to BCR to %r14) instruction by the if conversion pass. Also, fused compare-and-branch transform knows about conditional returns, emitting the proper fused instructions for them. This transform triggers on a *lot* of tests, hence the huge diffstat. The changes are mostly jX to br %r14 -> bXr %r14. Author: koriakin Differential Revision: http://reviews.llvm.org/D17339 llvm-svn: 265689
128 lines
2.8 KiB
LLVM
128 lines
2.8 KiB
LLVM
; Test 32-bit comparisons in which the second operand is zero-extended
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; from a PC-relative i16.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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@h = global i16 1, align 1, section "foo"
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; Check unsigned comparison.
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define i32 @f1(i32 %src1) {
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; CHECK-LABEL: f1:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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; Check signed comparison.
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define i32 @f2(i32 %src1) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: clhrl
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp slt i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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; Check equality.
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define i32 @f3(i32 %src1) {
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; CHECK-LABEL: f3:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: je
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp eq i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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; Check inequality.
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define i32 @f4(i32 %src1) {
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; CHECK-LABEL: f4:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: jlh
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@g
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%src2 = zext i16 %val to i32
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%cond = icmp ne i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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; Repeat f1 with an unaligned address.
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define i32 @f5(i32 %src1) {
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; CHECK-LABEL: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: clrjl %r2, [[VAL]],
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@h, align 1
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%src2 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src1, %src1
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br label %exit
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exit:
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%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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; Check the comparison can be reversed if that allows CLHRL to be used.
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define i32 @f6(i32 %src2) {
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; CHECK-LABEL: f6:
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; CHECK: clhrl %r2, g
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; CHECK-NEXT: jh {{\.L.*}}
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; CHECK: br %r14
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entry:
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%val = load i16 , i16 *@g
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%src1 = zext i16 %val to i32
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%cond = icmp ult i32 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i32 %src2, %src2
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br label %exit
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exit:
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%tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
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%res = add i32 %tmp, 1
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ret i32 %res
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}
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