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https://github.com/RPCS3/llvm-mirror.git
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938ff50eda
This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. llvm-svn: 236521
229 lines
6.8 KiB
LLVM
229 lines
6.8 KiB
LLVM
; Test v8i16 comparisons.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test eq.
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define <8 x i16> @f1(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vceqh %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp eq <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test ne.
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define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ne <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test sgt.
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define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vchh %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test sge.
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define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test sle.
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define <8 x i16> @f5(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f5:
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; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sle <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test slt.
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define <8 x i16> @f6(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f6:
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; CHECK: vchh %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test ugt.
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define <8 x i16> @f7(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f7:
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; CHECK: vchlh %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test uge.
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define <8 x i16> @f8(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f8:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v26
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp uge <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test ule.
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define <8 x i16> @f9(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f9:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v28
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; CHECK-NEXT: vno %v24, [[REG]], [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ule <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test ult.
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define <8 x i16> @f10(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
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; CHECK-LABEL: f10:
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; CHECK: vchlh %v24, %v28, %v26
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; CHECK-NEXT: br %r14
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%cmp = icmp ult <8 x i16> %val1, %val2
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%ret = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %ret
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}
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; Test eq selects.
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define <8 x i16> @f11(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f11:
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; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp eq <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test ne selects.
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define <8 x i16> @f12(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f12:
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; CHECK: vceqh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ne <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test sgt selects.
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define <8 x i16> @f13(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f13:
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; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sgt <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test sge selects.
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define <8 x i16> @f14(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f14:
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; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sge <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test sle selects.
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define <8 x i16> @f15(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f15:
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; CHECK: vchh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp sle <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test slt selects.
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define <8 x i16> @f16(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f16:
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; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp slt <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test ugt selects.
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define <8 x i16> @f17(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f17:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ugt <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test uge selects.
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define <8 x i16> @f18(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f18:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp uge <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test ule selects.
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define <8 x i16> @f19(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f19:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v24, %v26
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; CHECK-NEXT: vsel %v24, %v30, %v28, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ule <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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; Test ult selects.
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define <8 x i16> @f20(<8 x i16> %val1, <8 x i16> %val2,
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<8 x i16> %val3, <8 x i16> %val4) {
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; CHECK-LABEL: f20:
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; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v24
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; CHECK-NEXT: vsel %v24, %v28, %v30, [[REG]]
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; CHECK-NEXT: br %r14
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%cmp = icmp ult <8 x i16> %val1, %val2
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%ret = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
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ret <8 x i16> %ret
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}
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