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https://github.com/RPCS3/llvm-mirror.git
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1772a3e0bc
Summary: This fixes two related bugs. First, the generic optimization passes unfortunately generate negative constant offsets but the hardware treats SOffset as an unsigned value. Second, there is a hardware bug on SI and CI, where address clamping in MUBUF instructions does not work correctly when SOffset is larger than the buffer size. This patch works around this bug by never using SOffset. An alternative workaround would be to do the clamping manually when SOffset is too large, but generating the required code sequence during instruction selection would be rather involved, and in any case the resulting code would probably be worse. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96360 Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21326 llvm-svn: 272761
120 lines
4.9 KiB
LLVM
120 lines
4.9 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
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;CHECK-LABEL: {{^}}buffer_load:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
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;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
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;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
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;CHECK: s_waitcnt
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define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
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%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
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%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
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%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
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%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
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%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
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ret {<4 x float>, <4 x float>, <4 x float>} %r2
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs:
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;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:42
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
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;SICI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 offen
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;VI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1fff
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;VI: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:1
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_idx:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
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;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:58
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
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main_body:
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%ofs = add i32 %1, 58
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both:
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;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_both_reversed:
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;CHECK: v_mov_b32_e32 v2, v0
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;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
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main_body:
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0)
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ret <4 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x1:
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;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0)
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ret float %data
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}
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;CHECK-LABEL: {{^}}buffer_load_x2:
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;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
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;CHECK: s_waitcnt
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define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) {
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main_body:
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%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0)
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ret <2 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_negative_offset:
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;CHECK: v_add_i32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
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;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen
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define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
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main_body:
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%ofs.1 = add i32 %ofs, -16
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%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i1 0, i1 0)
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ret <4 x float> %data
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}
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declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0
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declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0
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declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0
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attributes #0 = { nounwind readonly }
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