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cdae83c48c
Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
185 lines
6.4 KiB
LLVM
185 lines
6.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}local_size_x:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[1].Z
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; CI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x1
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; VI-HSA: s_load_dword [[XY:s[0-9]+]], s[4:5], 0x4
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_x(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[1].W
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_y(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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; EG: MOV * [[VAL]], KC0[2].X
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; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN: buffer_store_dword [[VVAL]]
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define void @local_size_z(i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xy:
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
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; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VY]]
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; GCN: buffer_store_dword [[VAL]]
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define void @local_size_xy(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%val = mul i32 %x, %y
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xz:
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; HSA-DAG: s_and_b32 [[X:s[0-9]+]], [[XY]], 0xffff
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; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[X]], [[VZ]]
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; GCN: buffer_store_dword [[VAL]]
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define void @local_size_xz(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%val = mul i32 %x, %z
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_yz:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 1
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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; GCN: v_mul_u32_u24_e32 [[VAL:v[0-9]+]], [[Y]], [[VZ]]
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; GCN: buffer_store_dword [[VAL]]
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define void @local_size_yz(i32 addrspace(1)* %out) {
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entry:
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%val = mul i32 %y, %z
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store i32 %val, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_xyz:
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 1
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; SI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x6
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; SI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x7
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; SI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x8
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; VI-NOHSA-DAG: s_load_dword [[X:s[0-9]+]], s[0:1], 0x18
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; VI-NOHSA-DAG: s_load_dword [[Y:s[0-9]+]], s[0:1], 0x1c
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; VI-NOHSA-DAG: s_load_dword [[Z:s[0-9]+]], s[0:1], 0x20
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; GCN-DAG: v_mov_b32_e32 [[VY:v[0-9]+]], [[Y]]
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; GCN-DAG: v_mov_b32_e32 [[VZ:v[0-9]+]], [[Z]]
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; GCN: v_mad_u32_u24 [[VAL:v[0-9]+]], [[X]], [[VY]], [[VZ]]
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; GCN: buffer_store_dword [[VAL]]
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define void @local_size_xyz(i32 addrspace(1)* %out) {
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entry:
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%x = call i32 @llvm.r600.read.local.size.x() #0
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%y = call i32 @llvm.r600.read.local.size.y() #0
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%z = call i32 @llvm.r600.read.local.size.z() #0
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%xy = mul i32 %x, %y
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%xyz = add i32 %xy, %z
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store i32 %xyz, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_x_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define void @local_size_x_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.x() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_y_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define void @local_size_y_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.y() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_size_z_known_bits:
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; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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; GCN-NOT: 0xffff
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; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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; GCN-NEXT: buffer_store_dword [[VVAL]]
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define void @local_size_z_known_bits(i32 addrspace(1)* %out) {
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entry:
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%size = call i32 @llvm.r600.read.local.size.z() #0
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%shl = shl i32 %size, 16
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%shr = lshr i32 %shl, 16
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store i32 %shr, i32 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.local.size.x() #0
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declare i32 @llvm.r600.read.local.size.y() #0
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declare i32 @llvm.r600.read.local.size.z() #0
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attributes #0 = { nounwind readnone }
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