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https://github.com/RPCS3/llvm-mirror.git
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457501f033
Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
80 lines
3.3 KiB
LLVM
80 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s
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define void @coproc(i8* %i) nounwind {
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entry:
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; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4
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%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
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; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4
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tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
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; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1
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tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
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; CHECK: cdp p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: cdp2 p7, #3, c1, c1, c1, #5
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tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
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; CHECK: ldc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stcl p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2 p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
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; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
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tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
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; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
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; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
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%3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
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ret void
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}
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declare void @llvm.arm.ldc(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc(i32, i32, i8*) nounwind
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declare void @llvm.arm.stcl(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2(i32, i32, i8*) nounwind
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declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind
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declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
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declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
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declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
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declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind
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