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4265553ed8
When joining the legal parts of vector arguments into its original value during the lower of Formal Arguments in SelectionDAGBuilder, the Calling Convention information was not being propagated for the handling of each individual parts. The same did not happen when lowering calls, causing a mismatch. This patch fixes the issue by properly propagating the Calling Convention details. This fixes Bugzilla #47001. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D86715
120 lines
4.3 KiB
LLVM
120 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-LE
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; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-LE
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=SOFT
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=HARD
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-SOFT --check-prefix=FULL-SOFT-BE
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; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=FULL-HARD --check-prefix=FULL-HARD-BE
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define half @foo(half %a, half %b) {
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; SOFT-LABEL: foo:
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; SOFT: @ %bb.0: @ %entry
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; SOFT-NEXT: vmov s0, r0
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; SOFT-NEXT: vmov s2, r1
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; SOFT-NEXT: vcvtb.f32.f16 s0, s0
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; SOFT-NEXT: vcvtb.f32.f16 s2, s2
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; SOFT-NEXT: vadd.f32 s0, s0, s2
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; SOFT-NEXT: vcvtb.f16.f32 s0, s0
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; SOFT-NEXT: vmov r0, s0
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; SOFT-NEXT: bx lr
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;
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; HARD-LABEL: foo:
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; HARD: @ %bb.0: @ %entry
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; HARD-NEXT: vcvtb.f32.f16 s2, s1
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; HARD-NEXT: vcvtb.f32.f16 s0, s0
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; HARD-NEXT: vadd.f32 s0, s0, s2
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; HARD-NEXT: vcvtb.f16.f32 s0, s0
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; HARD-NEXT: bx lr
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;
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; FULL-SOFT-LABEL: foo:
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; FULL-SOFT: @ %bb.0: @ %entry
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; FULL-SOFT-NEXT: vmov.f16 s0, r1
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; FULL-SOFT-NEXT: vmov.f16 s2, r0
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; FULL-SOFT-NEXT: vadd.f16 s0, s2, s0
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; FULL-SOFT-NEXT: vmov r0, s0
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; FULL-SOFT-NEXT: bx lr
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;
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; FULL-HARD-LABEL: foo:
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; FULL-HARD: @ %bb.0: @ %entry
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; FULL-HARD-NEXT: vadd.f16 s0, s0, s1
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; FULL-HARD-NEXT: bx lr
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entry:
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%0 = fadd half %a, %b
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ret half %0
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}
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define <4 x half> @foo_vec(<4 x half> %a) {
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; SOFT-LABEL: foo_vec:
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; SOFT: @ %bb.0: @ %entry
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; SOFT-NEXT: vmov s0, r3
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; SOFT-NEXT: vmov s2, r1
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; SOFT-NEXT: vcvtb.f32.f16 s0, s0
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; SOFT-NEXT: vmov s4, r0
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; SOFT-NEXT: vcvtb.f32.f16 s2, s2
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; SOFT-NEXT: vmov s6, r2
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; SOFT-NEXT: vcvtb.f32.f16 s4, s4
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; SOFT-NEXT: vcvtb.f32.f16 s6, s6
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; SOFT-NEXT: vadd.f32 s0, s0, s0
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; SOFT-NEXT: vadd.f32 s2, s2, s2
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; SOFT-NEXT: vcvtb.f16.f32 s0, s0
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; SOFT-NEXT: vadd.f32 s4, s4, s4
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; SOFT-NEXT: vcvtb.f16.f32 s2, s2
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; SOFT-NEXT: vadd.f32 s6, s6, s6
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; SOFT-NEXT: vcvtb.f16.f32 s4, s4
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; SOFT-NEXT: vcvtb.f16.f32 s6, s6
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; SOFT-NEXT: vmov r0, s4
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; SOFT-NEXT: vmov r1, s2
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; SOFT-NEXT: vmov r2, s6
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; SOFT-NEXT: vmov r3, s0
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; SOFT-NEXT: bx lr
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;
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; HARD-LABEL: foo_vec:
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; HARD: @ %bb.0: @ %entry
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; HARD-NEXT: vcvtb.f32.f16 s4, s3
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; HARD-NEXT: vcvtb.f32.f16 s2, s2
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; HARD-NEXT: vcvtb.f32.f16 s6, s1
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; HARD-NEXT: vcvtb.f32.f16 s0, s0
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; HARD-NEXT: vadd.f32 s2, s2, s2
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; HARD-NEXT: vadd.f32 s0, s0, s0
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; HARD-NEXT: vcvtb.f16.f32 s2, s2
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; HARD-NEXT: vadd.f32 s4, s4, s4
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; HARD-NEXT: vcvtb.f16.f32 s0, s0
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; HARD-NEXT: vadd.f32 s6, s6, s6
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; HARD-NEXT: vcvtb.f16.f32 s3, s4
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; HARD-NEXT: vcvtb.f16.f32 s1, s6
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; HARD-NEXT: bx lr
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;
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; FULL-SOFT-LE-LABEL: foo_vec:
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; FULL-SOFT-LE: @ %bb.0: @ %entry
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; FULL-SOFT-LE-NEXT: vmov d16, r0, r1
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; FULL-SOFT-LE-NEXT: vadd.f16 d16, d16, d16
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; FULL-SOFT-LE-NEXT: vmov r0, r1, d16
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; FULL-SOFT-LE-NEXT: bx lr
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;
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; FULL-HARD-LE-LABEL: foo_vec:
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; FULL-HARD-LE: @ %bb.0: @ %entry
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; FULL-HARD-LE-NEXT: vadd.f16 d0, d0, d0
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; FULL-HARD-LE-NEXT: bx lr
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;
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; FULL-SOFT-BE-LABEL: foo_vec:
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; FULL-SOFT-BE: @ %bb.0: @ %entry
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; FULL-SOFT-BE-NEXT: vmov d16, r1, r0
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; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
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; FULL-SOFT-BE-NEXT: vadd.f16 d16, d16, d16
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; FULL-SOFT-BE-NEXT: vrev64.16 d16, d16
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; FULL-SOFT-BE-NEXT: vmov r1, r0, d16
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; FULL-SOFT-BE-NEXT: bx lr
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;
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; FULL-HARD-BE-LABEL: foo_vec:
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; FULL-HARD-BE: @ %bb.0: @ %entry
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; FULL-HARD-BE-NEXT: vrev64.16 d16, d0
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; FULL-HARD-BE-NEXT: vadd.f16 d16, d16, d16
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; FULL-HARD-BE-NEXT: vrev64.16 d0, d16
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; FULL-HARD-BE-NEXT: bx lr
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entry:
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%0 = fadd <4 x half> %a, %a
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ret <4 x half> %0
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}
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