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f65ec601b0
Fix the ARM backend's analyzeBranch so it doesn't ignore predicated return instructions, and make the MachineVerifier rule more strict. Differential Revision: https://reviews.llvm.org/D40061
32 lines
886 B
LLVM
32 lines
886 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-- -mcpu=cortex-a8 | FileCheck %s
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; Check that the peepholer removes dead instructions:
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;
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; vmov s0, r0
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; vmov r0, s0
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define void @t(float %x) nounwind ssp {
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; CHECK-LABEL: t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movw r1, #65534
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; CHECK-NEXT: movt r1, #32639
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: bxhi lr
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; CHECK-NEXT: .LBB0_1: @ %if.then
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; CHECK-NEXT: b doSomething
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entry:
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%0 = bitcast float %x to i32
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%cmp = icmp ult i32 %0, 2139095039
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @doSomething(float %x) nounwind
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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declare void @doSomething(float)
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