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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
107 lines
4.1 KiB
LLVM
107 lines
4.1 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the splitVecPredRegs pass in the Hexagon Peephole pass does not
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; move a vector predicate definition illegally, which ends up causing an assert
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; later. The assert occurs because there is a use of a register that does not
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; have a correct definition.
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define void @f0() local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b0
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br i1 undef, label %b2, label %b3
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b2: ; preds = %b1
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unreachable
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b3: ; preds = %b1
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br label %b4
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b4: ; preds = %b3
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br label %b5
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b5: ; preds = %b4
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br i1 undef, label %b13, label %b6
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b6: ; preds = %b5
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br label %b7
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b7: ; preds = %b6
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br label %b8
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b8: ; preds = %b7
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%v0 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> undef, i32 -1)
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br i1 undef, label %b9, label %b11
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b9: ; preds = %b8
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br label %b12
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b10: ; preds = %b12
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br label %b11
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b11: ; preds = %b10, %b8
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%v1 = phi <64 x i1> [ %v0, %b8 ], [ undef, %b10 ]
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%v2 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v1, <64 x i1> undef)
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%v3 = tail call <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1> %v2, <16 x i32> undef, <16 x i32> undef)
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%v4 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> undef, <16 x i32> %v3, i32 undef)
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%v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> undef, i32 undef)
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v5, <16 x i32> undef)
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%v7 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v6, <16 x i32> undef)
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%v8 = tail call <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32> %v7, <16 x i32> undef)
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%v9 = tail call <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32> undef, <16 x i32> %v8)
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%v10 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v9)
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%v11 = tail call <16 x i32> @llvm.hexagon.V6.vor(<16 x i32> %v10, <16 x i32> undef)
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%v12 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v11, i32 -1)
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%v13 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v12, i32 undef)
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tail call void @llvm.hexagon.V6.vmaskedstoreq(<64 x i1> undef, i8* undef, <16 x i32> %v13)
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unreachable
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b12: ; preds = %b12, %b9
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%v14 = phi i32 [ %v15, %b12 ], [ 0, %b9 ]
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%v15 = add nuw nsw i32 %v14, 1
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%v16 = icmp slt i32 %v15, undef
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br i1 %v16, label %b12, label %b10
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b13: ; preds = %b5
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
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; Function Attrs: argmemonly nounwind
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declare void @llvm.hexagon.V6.vmaskedstoreq(<64 x i1>, i8*, <16 x i32>) #2
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vor(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vsatwh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vshufoeb(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { argmemonly nounwind }
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