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69 lines
2.2 KiB
LLVM
69 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon -fp-contract=fast -enable-pipeliner < %s
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; REQUIRES: asserts
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; Pipelining can eliminate the need for a Phi if the loop carried use
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; is scheduled first. We need to rename register uses of the Phi
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; that may occur after the loop.
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define void @f0() #0 {
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b0:
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br i1 undef, label %b1, label %b12
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b1: ; preds = %b0
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%v0 = load float, float* undef, align 4
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br i1 undef, label %b2, label %b5
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b2: ; preds = %b1
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br i1 undef, label %b3, label %b4
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b3: ; preds = %b3, %b2
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br label %b3
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b4: ; preds = %b4, %b2
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br i1 undef, label %b5, label %b4
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b5: ; preds = %b4, %b1
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br i1 undef, label %b6, label %b9
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b6: ; preds = %b5
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br i1 undef, label %b7, label %b8
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b7: ; preds = %b7, %b6
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br label %b7
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b8: ; preds = %b8, %b6
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%v1 = phi i32 [ %v7, %b8 ], [ 2, %b6 ]
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%v2 = phi float [ %v6, %b8 ], [ undef, %b6 ]
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%v3 = phi float [ %v2, %b8 ], [ undef, %b6 ]
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%v4 = fmul float undef, %v2
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%v5 = fsub float %v4, %v3
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%v6 = fadd float %v5, undef
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%v7 = add nsw i32 %v1, 1
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%v8 = icmp eq i32 %v7, undef
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br i1 %v8, label %b9, label %b8
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b9: ; preds = %b8, %b5
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%v9 = phi float [ undef, %b5 ], [ %v2, %b8 ]
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%v10 = fsub float 0.000000e+00, %v9
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%v11 = fadd float %v10, undef
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%v12 = fmul float undef, %v11
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%v13 = fcmp ugt float %v12, 0.000000e+00
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br i1 %v13, label %b10, label %b11
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b10: ; preds = %b9
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br label %b11
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b11: ; preds = %b10, %b9
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%v14 = phi float [ undef, %b10 ], [ %v0, %b9 ]
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%v15 = fadd float undef, %v14
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br label %b13
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b12: ; preds = %b0
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ret void
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b13: ; preds = %b13, %b11
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br label %b13
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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